amitk3553 7 Report post Posted February 20, 2014 Why we use dynamic processes, exact role of dynamic processes? In place of these could we use simply static processes? Quote Share this post Link to post Share on other sites
Philipp A Hartmann 238 Report post Posted February 20, 2014 Why we use dynamic processes, exact role of dynamic processes? In place of these could we use simply static processes? Dynamic processes are especially used in situations when you need to spawn additional parallel execution in your model during the simulation. You cannot use static processes in such cases. /Philipp 1 amitk3553 reacted to this Quote Share this post Link to post Share on other sites
dakupoto 33 Report post Posted February 21, 2014 Dynamic processes are especially used in situations when you need to spawn additional parallel execution in your model during the simulation. You cannot use static processes in such cases. /Philipp In perfect agreement with what Phillipp has said, if one is trying to analyze/model hardware, absolutely do not use dynamic processes, as there is no such thing as creating hardware "on the fly". But if one is examing software, one could use dynamic processes. 2 rajit.a and amitk3553 reacted to this Quote Share this post Link to post Share on other sites
David Black 155 Report post Posted February 26, 2014 Dynamic processes have many uses. An interesting example is for those modeling cell phone base station environment. When a cell phone "comes into range", you can launch a process to model the appearance of a cell phone, and have it die when it goes out of range. Another example might be to model hot pluggable USB devices on a USB controller. Admittedly, you could create a pool of static processes for this purpose, but it is not always a natural style. For verification, dynamic processes are frequently useful to do activities related to temporal assertions (i.e. like System Verilog Assertions or PSL). There is an overhead for launching dynamic processes that has to be considered when modeling, so only use when it makes sense. SystemVerilog has the construct: fork/join_none that is the equivalent concept to spawning in SystemC. Quote Share this post Link to post Share on other sites