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Everything posted by amitk3553

  1. Hello, With the following example, I have a method which is sensitive to an event which is notified(immediately) from end_of_elaboration() function. This gives Segmentation fault (core dumped). However if I do func_event.notify(SC_ZERO_TIME); or func_event.notify(1,SC_NS), there is no Segmentation fault #include "systemc.h" class TOP : public sc_module { public: sc_event func_event; SC_HAS_PROCESS(TOP); TOP(sc_module_name name) { SC_METHOD(method_function); sensitive<<func_event; dont_initialize(); } void end_of_elaboration(){ func_event.notify(); } void method_function() { std::cout<<"inside f() before wait"<<std::endl; } }; int sc_main(int argc, char* argv[]) { TOP top("top"); sc_start(); return 0; } Please have a look, thanks in advance.
  2. I want to create VCD file at different location than the directory containing executable. Could I pass the intended path of location for VCD file creation into sc_create_vcd_trace_file("/c/users/xyz/abc") Please give your comments. Thanks.
  3. What does mean by bug of glitch. How can we remove it?
  4. In multi ports we can bind no of initiators to single target socket init_1 ---- init_2 ---- ------- target_socket init_3 ---- in tagged sockets what i understood no of interface method calls on sockets with tagged id to indicate through which socket transaction is coming on single target socket Means difference in multiports and tagged sockets is in tagging. Like in tagged sockets we use ids to indicate the socket through which they come then it would be possible in multiports to use multi port index to know that from which socket, transaction had come. Or TAGGED SOCKETS AND MULTIPORTS ARE SAME CONCEPT except multi port index as tag in MULTIPORTS id as tag in tagged sockets Then What is difference in use-cases of both?
  5. What is the purpose of passing time in b_transport method call in below code? trans.set_data_ptr(data_ptr_host_hci_drive); sc_time to(SC_ZERO_TIME); init_socket->b_transport(trans, to); And what is the meaning of underlined portion in constructor line? hci_ll_monitor(sc_module_name nm): sc_module(nm),
  6. What are the differences in IP level and SOC level Verification? Which kind of difficulties we face in SOC level Verification as compared to IP level verification?
  7. Why we use dynamic processes, exact role of dynamic processes? In place of these could we use simply static processes?
  8. Where is the use of the concept of polymorphism in testbench development in UVM. Please tell me some usecases of polymorphism in testbench development.
  9. In I2c u would be having suppose 4 clocks. You would implement four clocks in systemC initially using sc_clock construct, then u have to do anding of four clocks to generate single synchronised clock.
  10. Hello sam, May be its possible through UVM connect. i donot know much about it, but if u explore it, u can find some solution. Regards cam
  11. thanks karandeep, Could somebody throw light on daisy chain equation? Regards cam
  12. ok, do u know about anything in UVM model of any IP, which we can use in modeling of that IP in systemC. Something common in systemC model and model in UVM for same IP?
  13. In section 10.1, there are differences Regarding to 1) TLM generic payload 2) Timing annotation 3) const and non const reference One thing, what is about (ports, exports) and sockets. concept of sockets is related to TLM or its in systemC?
  14. Is there some use of TLM 2.0 concepts in UVM?
  15. I had developed some model(Predictor) in System Verilog in UVM testbench. So Could i use something from existing model into development of SystemC model?
  16. What is the purpose to make virtual platforms? It just mimics the functionality of hardware?In case if we have hardware,then what is the purpose of virtual plate forms? What are things we explore in architectural exploration?How we do that?
  17. There are two terms that are added in TLM1.0 to make it TLM2.0? 1) Sockets 2) generic payload Is there are more terms to differentiate TLM 1.0 and TLM 2.0.?
  18. What is the difference between configuration object and configuration space in UVM?
  19. Please brief the differences b/w ovm and uvm or the modifications done in ovm to develop uvm.
  20. What is constraint solver in SV? What is the meaning of statement if we say that "SV is having powerful constraint solver"?
  21. Thanks, One more doubt about "module (design) can not call task/function inside a program block. But a program can call task/function inside module (design)" It means we cannot make instance of module in program block and can make instance of Program block in Module?
  22. What is the meaning of following "module (design) can not call task/function inside a program block. But a program can call task/function inside module (design)" Please explain it!! Thanks
  23. "Since SystemC contains no guaranty about the order in which processes runnable in the same delta cycle are executed, a model like the example leads to non-deterministic behavior", but there would be something in SystemC to make processes run one after another. Like I want process P1 run first, and then P2 p1(){ wait(ev1); cout << "wait done"; } p2(){ ev1.notify(); } I had registered both in constructor, where they will run concurrently, this way according to you, may be process P2 run first and then P1, but want P1 first then how it would be possible?? Yes alan, I had used loops in threads.
  24. Constructor part in my code hci_top(sc_module_name nm):sc_module(nm), ll_hci_tar_socket("ll_hci_tar_socket") { SC_THREAD(hci_ll_cmd_pkt_transmit); hci_ll_cmd_thread = sc_get_current_process_handle(); ll_hci_tar_socket.register_b_transport(this, (&hci_top::hci_host_pkt_transmit)); } In hci_host_pkt_transmit, i have notified an event like evt_1.notify(); And I am waiting on this event in hci_ll_cmd_pkt_transmit like wait(evt_1); But wait is never ending, means evt_1 is not coming? Had I done something against scheduler operation here?
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