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VCS problem with SystemVerilog

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I am now running into one problem about VCS. Now give a simple descripton about it, I use VCS201209 to compile pieces of verification code, there is no any compiling error,but run time error appears. The code is as follows:
            1868 //pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}}; // change because of the run time error
            1869 if ((`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)) == 0) begin
            1870   pcie_item.first_be = {(length % `DW_BYTE_COUNT){1'b1}};
            1871 end     
            1872 else begin
            1873   pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}};
            1874 end

`DW_BYTE_COUNT=4; `FDW_BE_WIDTH=4, length is one bit_stream type variable. line 1868 has been commented, changed to line 1869-1874. The reason why i change it is that there is such a run time error:
../sv/04_ref_model/ref_model.sv, line 1868: ** OTENF: S QOP_CONCAT (S,S) /* {} */
Note: OTENF is an internal error meaning Op_Table Entry Not Found
Assertion failed " Note: Set environment variable VCS_REPORT_ALL_OTENF to get all the OPTENF errors." at line 711 in file fun.c

An unexpected termination has occurred in /EDA_Tools/synopsys/vcs1209/linux/bin/vcs1

at ../sv/04_ref_model/ref_model.sv, 1730
During Codegen 
During Pass2 Module vcs_paramclassrepository Module vcs_paramclassrepository

--- Stack trace follows:
[Thread debugging using libthread_db enabled]
[New Thread 0xf7be9bb0 (LWP 24498)]
0xffffe405 in __kernel_vsyscall ()

Thread 2 (Thread 0xf7be9bb0 (LWP 24498)):
#0  0xffffe405 in __kernel_vsyscall ()
#1  0x00aebb26 in pthread_cond_wait@@GLIBC_2.3.2 () from /lib/tls/libpthread.so.0
#2  0x0aee7e64 in ?? ()
#3  0x00ae9371 in start_thread () from /lib/tls/libpthread.so.0
#4  0x00a41ffe in clone () from /lib/tls/libc.so.6
Backtrace stopped: Not enough registers or memory available to unwind further

Thread 1 (Thread 0xf7fd2700 (LWP 24497)):
#0  0xffffe405 in __kernel_vsyscall ()
#1  0x00a0447b in waitpid () from /lib/tls/libc.so.6
#2  0x009ae349 in do_system () from /lib/tls/libc.so.6
#3  0x009ae6c1 in system () from /lib/tls/libc.so.6
#4  0x00aef78d in system () from /lib/tls/libpthread.so.0
#5  0x0b3bc389 in tracker::StackAnnotator::getGdbOutput(char const*, char const*, char const*) ()
#6  0x0b3bd677 in tracker::StackAnnotator::dumpProcessStack(unsigned int, char const*, char const*) ()
#7  0x0b3b29c6 in dumpStackTrace ()
#8  0x0b3b74e7 in vcsAssertNoReturn ()
#9  0x08fbbf0d in ?? ()
#10 0x08fbc1c8 in BuildFUNsForRout ()
#11 0x0907ff8c in BuildMOPsForRout ()
#12 0x08f4e069 in ?? ()
#13 0x08f4f12e in ?? ()
#14 0x08f52423 in CodeGenC ()
#15 0x09187f31 in Phase234 ()
#16 0x08806fba in ?? ()
#17 0x088214ab in ?? ()
#18 0x088238ee in DoPass2 ()
#19 0x0876b5ab in doGAToPass2 ()
#20 0x0876be7a in c_main ()
#21 0x09293842 in main ()
Completed context dump phase location* 'Module' 'Module'
CPU time: 33.817 seconds to compile
make: *** [comp] Error 255

I have done the error analysis, my concept is that maybe the reason is that the value of `FDW_BE_WIDTH - (length % `DW_BYTE_COUNT) has the possibility of zero. So I add the judge condition about the value of `FDW_BE_WIDTH - (length % `DW_BYTE_COUNT), but it still reports the same error about line 1873. If I comment line 1873, the error disappears. It seems like that the problem has something to do with the action of compiler's analyzing the code.


Could any expert give me some information?

Thanks in advance.

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System Verilog spec requires the "left operand" of a replication expression to be a compile time constant expression.

Meaning, if you write { C {1'b1} } then C should be a constant expression.


In your code, the left operand is some function of "length", which I guess is not a constant - therefore the code is invalid.

Unfortunately it seems that VCS fails to handle this error correctly - it probably outputs some WUIMCM warning - look in your logs.

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