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zcahana

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Everything posted by zcahana

  1. Hierarchical references, including references to elements of an array of interfaces, require constant expressions as array indices. On the other hand, arrays of virtual interfaces don't require it, and these are also assignment compatible with arrays of interfaces. Thus, you may use the following trick: duv_sigif fifo_if[`PORTS_NUM] (clk, rst); duv_vif fifo_vif[`PORTS_NUM] = fifo_if;
  2. If you require to be unaware of the width of your vector, you can use this: doubler #($bits(A))::double(A); Yes, its quite a verbose (and ugly) syntax, but on the other hand, VHDL is quite verbose (and ugly ) as well... Regarding SV lacking this feature - well, it does make sense to me, at least when considering simulators performance (static vs. dynamic arrays, optimization, etc...) On the other hand, the language does enable you to use dynamic arrays. Moreover, you may quite easily convert them to packed vectors with the streaming operator.
  3. Hi, Your problem is actually twice than you think - you must use a constant width both in the part select expression and in the replication expression: addr[ const_or_var : const ] = { const { const_or_var } }; The trivial solution would be to loop through the target vector and assign its bits the value you need. For example: for (int i = 0; i < idx_bits; i++) addr[i] = 1'b1; Of course, if you expect a wide part select and want to reduce the number of iterations, you may assign such a code: int idx_bytes = idx_bits / 8; for (int i = 0; i < idx_bytes; i++) addr[i*8 +: 8] = { 8 {1'b1} }; for (int i = idx_bytes * 8; i < idx_bits; i++) addr[i] = 1'b1; Hope that helps.
  4. Well, there are no dynamic packed arrays in System Verilog. If the logic of your function is independent of the width of the data, as in your example, then you can use a parameterized class that supply you with the required function. For example: class doubler #(int unsigned WIDTH = 1); static task double(ref [WIDTH-1:0] val); val = val * 2; $display("%b",val); endtask endclass module test; logic [3:0] A; logic [7:0] B; initial begin A = 3; doubler #(4)::double(A); B = 5; doubler #(8)::double(; end endmodule
  5. Hi, In Object Oriented Programming, each class defines a set of public methods and/or fields ("API"), thus giving an interface to the services and/or data available from objects of that class. Best practices suggest that fields should normally be inaccessible from outside the class, thus allowing classes to separate interface & implementation (or representation). Moreover - in System Verilog, variables defined inside functions/tasks are accessible only from within that function/task, and definitely not from within other classes. Methodologically speaking, you don't want your monitor to be dependant on your driver; The monitor should be able to independently run when the agent is in passive mode (i.e. no active driving of the interface, only passive monitoring). Try to find a way to extract the information you need from the monitored interface itself: For example, accumulate the packet's payload passed on the interface into a queue of bytes, and use queue.size() method to get its bytecount.
  6. Looks like VCS doesn't support class specializations with the event datatype. My suggestion is to use uvm_event class to achieve the required functionality. See here for class description: http://www.dvteclipse.com/uvm-1.1-HTML_API/uvm_pkg-uvm_event.html
  7. Hi, Given that all of your agents use the same sequence item, you can connect (@ connect_phase) each of the agents' analysis ports to a single analysis export/imp in the scoreboard. That'll work, and easy to implement. A better and more general approach is to implement a many-to-one "adapter" of analysis ports, then connect all agents to the "many" side of the adapter, and the "one" side of the adapter to the scoreboard. If your agents use different sequence items, but your scoreboard applies a uniform logic to all of them, then you can have in your scoreboard a single analysis imp, parameterized to a common base class of your sequence items (e.g. uvm_sequence_item). In this case you'll still need to implement some "adapting" in order to connect an analysis port of type <derived> to an analysis port of type <base>.
  8. Hi, System Verilog spec requires the "left operand" of a replication expression to be a compile time constant expression. Meaning, if you write { C {1'b1} } then C should be a constant expression. In your code, the left operand is some function of "length", which I guess is not a constant - therefore the code is invalid. Unfortunately it seems that VCS fails to handle this error correctly - it probably outputs some WUIMCM warning - look in your logs.
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