problem about macro `uvm_analysis_imp_decl

[mrforever]

Hi, experts,

There is several drivers and one subscriber. I put one uvm_analysis_port in each driver and several imps in the subscriber via using macro `uvm_analysis_imp_decl(_a), `uvm_analysis_imp_decl(_b, etc.

Also Implement functions write_a(), write_b(), etc. write_a() and write_b() have different processing logic. Then, the uvm_analysis_port in each driver invokes one of the functions write_a(), write_b(), etc.

 

But the VCS reports such an error:

 

Could not find member 'write_a' in class 'uvm_analysis_port', at

  "/EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/tlm1/uvm_analysis_port.svh",

 

Is there anybody to handle my problem? Thanks in advance!

[apfitch]

You should be calling write() in the analysis_port, not write_a - the analysis_imp automatically translates your call to write to write_a and so on,

 

regards

Alan

[mrforever]

You should be calling write() in the analysis_port, not write_a - the analysis_imp automatically translates your call to write to write_a and so on,

 

regards

Alan

 

Alan, thanks for your reply. I have using uvm_analysis_tlm_fifo instead of uvm_analysis_imp_decl. Hope it will work well.

[apfitch]

Just one "gotcha" - remember that uvm_tlm_analysis_fifo stores references, so you should make a copy of your transaction to put in the fifo,

 

regards

Alan

[mrforever]

Just one "gotcha" - remember that uvm_tlm_analysis_fifo stores references, so you should make a copy of your transaction to put in the fifo,

 

regards

Alan

 

Thanks, Alan. I am doing it using such a way

 

regards

mrforever