Jump to content

Search the Community

Showing results for tags 'imp'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM 2017 - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
    • UVM 1.2 Public Review
  • Portable Stimulus
    • Portable Stimulus 1.0
    • Portable Stimulus Pre-Release Discussion
  • IP Security
    • IP Security Assurance Whitepaper Discussion
  • IP-XACT
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests


Biography


Location


Interests


Occupation


Company

Found 1 result

  1. Hi, experts, There is several drivers and one subscriber. I put one uvm_analysis_port in each driver and several imps in the subscriber via using macro `uvm_analysis_imp_decl(_a), `uvm_analysis_imp_decl(_b, etc. Also Implement functions write_a(), write_b(), etc. write_a() and write_b() have different processing logic. Then, the uvm_analysis_port in each driver invokes one of the functions write_a(), write_b(), etc. But the VCS reports such an error: Could not find member 'write_a' in class 'uvm_analysis_port', at "/EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/tlm1/uvm_analysis_port.svh", Is there anybody to handle my problem? Thanks in advance!
×
×
  • Create New...