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Why use virtual word in declaration of a class?

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Dear all, can anyone plz tell me, why do we use 'virtual' word in the declaration of every class in UVM library when it is inherited.?

Ex: virtual class uvm_test extends uvm_component

So why this virtual word is used here? Whats the meaning of this virtual. Any guidance would be appreciated.


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This is related to polymorphism, google for 'systemverilog polymorphism' and you'll find many good answers for that. An Example is to create a class 'car' which has a virtual method (functions in classes are called methods) 'WhoAmI' that returns "I'm a car". Later you extend this class to create 'toyota' which is a child class to 'car'. This child class has the same method 'WhoAmI' but it returns "I'm a toyota". When using these classes, you can instantiate a 'car' and assign it a 'toyota' (because a toyota is a car) and if you call WhoAmI, it will return "I'm a toyota", even though you have instantiated a 'car'.

Edited by whiteriver
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take rajneeshT's explanation for virtual class, my explanation was about virtual methods inside a class, which is not the same thing.

The example on virtual classes is to have a placeholder for the class structure, you can declare variables and methods on the virtual class, but as rajneeshT said, you can't instantiate it directly, so you have to extend it and then instantiate the child classes.

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swapnilm, It is possible you are looking at the Accellera SV 3.1a LRM which does not explain this topic very well. (It is hard for me to believe it is now 9 years old) It does not mention the relationship between virtual classes and pure virtual methods at all. The IEEE 1800-2005 LRM clarified this, and the 1800-2009 LRM is the most current, with the 1800-2012 LRM just about to be published.

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