
DavidLarson
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Everything posted by DavidLarson
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For 1: You can use the schema files provided by Accellera. Run them with xmllint. For 2: No. Pretty sure there isn't an open-source tool to do that for you.
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Referencing the memoryMap of a sub-component
DavidLarson replied to ddc1234's topic in IP-XACT Discussion
Forget my last question. I believe I figured it out. Now to figure out how to put hdl_paths in a hierarchy.... -
Referencing the memoryMap of a sub-component
DavidLarson replied to ddc1234's topic in IP-XACT Discussion
Thank you Erwin. Yes that does help. Our situation is a little different, where we have a hierarchy of components, each with their own bank of registers. So, we won't be looking to connect sibling components, but connections would be from parents to children. Can that be done with IPXACT? -
Referencing the memoryMap of a sub-component
DavidLarson replied to ddc1234's topic in IP-XACT Discussion
Hi Erwin, Thank you for the info. I've been reading through the User Guide and it doesn't seem to provide all the info I need to do this. For example, in section 3.1.6 it says: Yet, it doesn't explain how to put a memoryMap in an addressSpace. You can only put segments in addressSpaces, not memoryMaps. Can you please provide an example of what that would look like? Regards, David -
SystemVerilog/UVM linting - what tools exist ?
DavidLarson replied to ljepson74's topic in UVM Simulator Specific Issues
I'm going through the HAL documentation and it looks l like the only languages that HAL supports are: Verilog, VHDL, SystemC and e. No system verilog. Rats. -
uvm_reg_field W1C/W0S update problem
DavidLarson replied to saxmanlogic's topic in UVM (Pre-IEEE) Methodology and BCL Forum
I have found a related problem. When you need to send a 1 to a W1C register field, the normal flow doesn't work: register_model.register.w1c_field.set(1); // <--- this is set to 0 internally register_model.register.update(status); This is clearly not what the user expects. What is the correct flow for these registers? -
Problem with uvm_object_utils
DavidLarson replied to ggupta's topic in UVM (Pre-IEEE) Methodology and BCL Forum
I just compiled your code (I added the endclass keyword): class addr_hole_seq extends uvm_sequence # (uvm_sequence_item); `uvm_object_utils(addr_hole_seq) endclass and it compiled fine. Now you need to check elsewhere ... the code preceding this, how you are compiling, etc. -
Problem with uvm_object_utils
DavidLarson replied to ggupta's topic in UVM (Pre-IEEE) Methodology and BCL Forum
I see errors like this when the macro is not called correctly. Check these: If the object is parameterized you should be using `uvm_object_param_utils (<object_name>#(<parameters>)). make sure that the argument to the macro contains the name of the class and there are no typos. Make sure the registration macro isn't called more than once. Other than that, it would be helpful to see your source code. -
The uvm_config_db is used primarily to configure uvm_components. This is a snippet from the reference manual (italics are mine): The uvm_config_db class provides a convenience interface on top of the uvm_resource_db to simplify the basic interface that is used for configuring uvm_component instances. Regardless, I find that it is far better to set the variable directly. The real power of the resource DB is when the wildcard can be used in the path, but that doesn't apply to you in this case.
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Hi mrforever, I'm not sure if I understand your question correctly. It sounds to me that the forever loops in the monitor and sequence are intentional (not bugs)? So the sequence is sending background traffic? If so, then I would be sure that your sequence is not issuing objections. The monitor will continue to issue objections (raising at the beginning and dropping at end of the transaction), but that shouldn't prevent the test from ending, because as soon as the last transaction completes then all of the objections will be dropped. I would also be sure that you aren't setting a drain tim
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Hello, I am using the uvm_heartbeat object in my test bench and found that it always watches for all objection activity under the context component. By definition, it should only watch for the list of components registered to it. I found this when registering only one component to watch (my interrupt handler) and even after the component had no activity long after several heartbeat windows, a fatal HBFAIL message was not issued. Digging into the source code, I can see that the heartbeat keeps track of which components are registered by populating an associative array, like this:
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uvm_random_stimulus usage
DavidLarson replied to kumarv's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi kumarv. This is a great question. This class does indeed look very VMM-ish. I haven't used the class before, but I'd like to see if I could use it as my test case somehow (that seems to be the usage model), though test cases should be extended from uvm_test, not from uvm_random_stimulus. I'll play around with it. -
uvm_mem_single_walk_seq
DavidLarson replied to DavidLarson's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi Peter, Wouldn't setting byte_addressing to 1 configure the map to be addressed on a byte-boundary? Don't we want the addresses to be n_bytes apart (set to 0)? Thanks, David -
uvm_mem_single_walk_seq
DavidLarson replied to DavidLarson's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi Peter, The tool we are using creates this call to create_map(): default_map = create_map("", 0, 4, UVM_BIG_ENDIAN, 0); Does that help? Thanks! -
uvm_heartbeat
DavidLarson replied to R_C1363912821's topic in UVM (Pre-IEEE) Methodology and BCL Forum
There is a new paper on this topic that steps you through how to use the heartbeat: http://www.uvmworld.org/contributions-details.php?id=218&keywords=Mastering_UVM:_UVM_Heartbeat -
I am currently running the built-in uvm_mem_single_walk_seq on an internal RAM. The sequence is really nice, but there does seem to be one glitch with it. It loops through all addresses of the RAM from the beginning to the end, ~incrementing by 1~. This mode isn't supported in our RAM because addresses must be incremented by 4. Am I using the seq incorrectly somehow? If not, then is it possible to change the sequence to have the increment value be programmable (using the uvm_resource_db)? Thanks!