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Hash1

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3
Joined
April 4, 2013
Last visited
July 11, 2014

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Everything posted by Hash1

UVM_FATAL Errors

Hash1 replied to Hash's topic in UVM SystemVerilog Discussions

Yes, Have fixed the issue!
- April 9, 2013
- 10 replies
VCS problem with SystemVerilog

Hash1 replied to mrforever's topic in UVM SystemVerilog Discussions

I would recommend -send the stack trace to vcs_support@synopsys.com
- April 8, 2013
- 1 reply
- - vcs
  - systemverilog
  - (and 1 more)
    Tagged with:
    
    vcs
    
    systemverilog
    
    complie
problem about multiple sequencers which have the same name

Hash1 replied to mrforever's topic in UVM (Pre-IEEE) Methodology and BCL Forum

Hi can share what is the fix here? -Thanks
- April 4, 2013
- 3 replies
- - multiple
  - sequecers
  - (and 1 more)
    Tagged with:
    
    multiple
    
    sequecers
    
    unique

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