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dave_59

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  1. Haha
    dave_59 got a reaction from u24c02 in Regarding the UVM field automation macros   
    There have been some improvements to the performance of the field automation macros, but I still do not believe their benefit is worth the cost. You should be able to prove it to yourself by creating a simple testbench with and without the macros.
  2. Like
    dave_59 got a reaction from tudor.timi in Rnadomize a variable inside a function   
    The reason for the failure is because of the bad constraint. Since the call to randomize is outside of a class declaration, std::randomize() gets called implicitly.
  3. Like
    dave_59 got a reaction from karandeep963 in Cross coverage of two covergroups   
    This is just hypothetical, not real SV syntax. I answered this question here: https://verificationacademy.com/forums/coverage/cross-coverage-two-covergroups
  4. Like
    dave_59 got a reaction from karandeep963 in Constraining Sequencer from testcase   
    You may want to look at the new soft constraint feature of SV1800-2012. A soft constraint is automatically disabled when there is a conflicting constraint. However, then you lose a way of describing your intent. Did you intend to disable the constraint with a new one, or did you add a conflicting constraint by mistake and now you will no longer get an constraint failure.
  5. Like
    dave_59 got a reaction from Parth in Multithread and automatic variable   
    bhunter, that is incorrect; only case 1 will work. The initialization of automatic variables happens as the scope they declared in come into existance(activated).
     
    Each iteration of the for loop creates a new fork/join_none block with a unique value of i.  That unique value of i is used to initialize the local copy of j created for each fork/join_none block. If you put the variable assigment into procedural code of the child threads, the ordering of the execution of those child threads are indetermiate, and at best, deferred until the parent thread blocks or terminates.
  6. Like
    dave_59 got a reaction from Hany Salah in UVM in Questasim   
    I answered this here.
  7. Like
    dave_59 got a reaction from amitk3553 in Program blocks   
    Modules are used for both design and verification. Modules are instantiated to create hierarchy of other modules, interfaces and programs. Programs cannot contain any hierarchy. Just forget about programs.
  8. Like
    dave_59 got a reaction from ulfat in UVM Simulation inquestasim 10.0b version   
    Please copy the file to the correct location if you install 10.0c and use UVM. With later releases the file should be in the correct place.

    The missing files are:
    <install>/<uvm_dir>/win32/uvm_dpi.dll
    The <uvm_dir> names are: uvm-1.0p1, uvm-1.1 and uvm_reg-1.1.

    The files are located at:
    <install>/win32/<uvm_dir>/uvm_dpi.dll
    Please copy the files to the correct location:
    <install>/<uvm_dir>/win32/
  9. Like
    dave_59 got a reaction from chandan in Questasim with Cygwin   
    From my perspective, I consider the first release of the UVM 1.0p1 a beta release. I strongly suggest you move to 1.1 or later (1.1c was released a month ago).
  10. Like
    dave_59 got a reaction from chandan in Questasim with Cygwin   
    You don't need the -sv_lib switch when using the UVM package that comes with Questa.
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