uwes
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Everything posted by uwes
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Calling grandparent's method and not parent's
uwes replied to grai's topic in UVM (Pre-IEEE) Methodology and BCL Forum
hi, isnt the classtype::method() only valid for static members? -
uvm_test_done.raise_objection(target_comp);
uwes replied to sudheer59's topic in UVM Simulator Specific Issues
did you import uvm_pkg::* ? -
use pack_bytes instead of pack
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hi, why not module test187; import uvm_pkg::*; `include "uvm_macros.svh" class ac extends uvm_object; rand bit[3:0]a; rand bit[121:0]b; rand bit[162:122]c; rand bit[511:163]d; `uvm_object_utils_begin(ac) `uvm_field_int(a,UVM_DEFAULT) `uvm_field_int(b,UVM_DEFAULT) `uvm_field_int(c,UVM_DEFAULT) `uvm_field_int(d,UVM_DEFAULT) `uvm_object_utils_end function new (string name=""); super.new(name); endfunction endclass class bc extends uvm_object; rand bit[511:0]field; `uvm_object_utils(bc) function new (string name=""); super.new(name); endfunction endclass initial begin ac ma = new; bc mb = new; bit d[]; ma.pack(d); $display({>>{d}}); end endmodule
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hi, the path would be to define a new object deriving from uvm_object holding the additional properties. a configured instance can then be passed via the <uvm_reg>.write/read/update/mirror function in the "extension" argument. in the reg-to-bus adapter.reg2bus() translation stage you can refer to the passed object as "get_item().extension" and you can adjust the properties of your low level sequence.
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Simulation blocked at waiting statement in main_phase
uwes replied to jhpark's topic in UVM Simulator Specific Issues
hi, no-one is objecting the end-of-main phase. therefore the phase tasks of your agents (especially the one of main_phase) are killed shortly after starting. -
random variable of type bit with varying width
uwes replied to meenu's topic in UVM (Pre-IEEE) Methodology and BCL Forum
why not simply randomize an instance of a uvm_reg_data_t and constrain it to have at most n bits (or simply randomize full and mask the reset away) ? -
referencing an array of uvm_analysis_imp in a scoreboard
uwes replied to makers78's topic in UVM SystemVerilog Discussions
what about the following path: (better then the _decl macros) ----- class listener #(type E,T) extends uvm_subscriber #(T); local int idx; function new(string name, E parent,int idx); super.new(name,parent); this.idx=idx; endfunction // new function void write(input T t); E p; $cast(p,parent); p.writeit(t,idx) endfunction endclass then make your array of subscribers and new it with the idx. /uwe -
hi, if im not mistaken 10.20s100+ runs fine with uvm11a
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IUS92 supports process and virtual classes BUT UVM11 has not been qualified on IUS92 (there are known issues). >Is there any method to make IUS92 sim uvm1.1 obviously you could backport, create workarounds but what for?, the world has turned since 9.2 - you got the 10.20 stream or the more recent 11.10 stream and soon the 12.10stream which all run UVM10+. if you want latest UVM you should be also using the latest simulator :-)
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members labeled m_* are typically fields/tasks/functions which should be considered internal/implementation dependent and are not part of the UVM standard. they are subject to change at any time without notice or deprecation process. no user code should be using any m_* coming from the uvm_pkg. the standard+library reference also should not have references to any m_* field/member. why is that: the reason for this is that sv doesnt have "friend" modifiers like c++ has (http://www.cplusplus.com/doc/tutorial/inheritance/). basically the externally visible api of a sv class is the same for ALL other classes. you cant distinguish between code which can access certain members and classes which cannot access certain members.
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NO Components instatiated (UVm, IUS 11.2)
uwes replied to digesh055's topic in UVM (Pre-IEEE) Methodology and BCL Forum
i still would bet that this is simply an invocation issue. if this is a script switch on command trace (set verbose or set -x) if this is a make (make -n). also double check that the option preceeding +UVM_TESTNAME=foo is not an option taking an arg and you didnt supply that arg (if so +UVM_TESTNAME=foo becomes the arg to the ius invocation option) /uwe -
NO Components instatiated (UVm, IUS 11.2)
uwes replied to digesh055's topic in UVM (Pre-IEEE) Methodology and BCL Forum
please supply more details or file a ccr with cadence support.im not aware of issues in that area. please check for any other messages (such as disabled DPI) or scripting issues. -
Running a parameterized test
uwes replied to grai's topic in UVM (Pre-IEEE) Methodology and BCL Forum
yes, i know - however it gives a string "my_test" which can be used as the type key in the factory (unless as you say there are multiple specializations) -
Running a parameterized test
uwes replied to grai's topic in UVM (Pre-IEEE) Methodology and BCL Forum
the shortcut for the code above is: `uvm_component_registry(my_test#(item_t, NUM_ANALYSIS_PORTS), "my_test") -
Seq.start on indexed component
uwes replied to digesh055's topic in UVM (Pre-IEEE) Methodology and BCL Forum
you have to supply a reference to a sequencer as first arg to seq.start and not a sequence-ref nor a string. -
Ensuring users call super.function()
uwes replied to mastrick's topic in UVM SystemVerilog Discussions
yes, basically you got two options: 1. a local flag identifying correct super.function usage (set when super.function is invoked, checked when used) 2. use a linter which is capable to check super.function invocation /uwe -
Running a parameterized test
uwes replied to grai's topic in UVM (Pre-IEEE) Methodology and BCL Forum
hi, you cant refer to parameterized class via a string type name directly.there are several ways to resolve that. 1. you could register a string name for the param type in the factory 2. you could create a non-param test class instantiating your param test class and then use the non-param class with +UVM_TESTNAME 3. you could derive a non-param class from your param class and reference that /uwe -
NO Components instatiated (UVm, IUS 11.2)
uwes replied to digesh055's topic in UVM (Pre-IEEE) Methodology and BCL Forum
well, there are several causes: - you have a typo and didnt use +UVM_TESTNAME=test_name on the commandline - your test with the name "test_name" is not present (different name or typo) or has not been registered with the factory - you didnt compile the class test_name (forgot to compile/include) -
calling run_test() at no-zero time
uwes replied to jithinraj1989's topic in UVM SystemVerilog Discussions
uvm doesnt allow time being spend before run_test(). anything between run_test() and run_phase() basically builds the static infrastructure/topology - then real wall clock time is spend with the created instances. so please describe your use model and i'm this also fits into the uvm infrastructure -
that is an SV limitation around parameterized types. what might work as a workaround is to look at get_type_name() or $typename() and trying to extract the typename from it. /uwe
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UVM Factory override and compilation issue
uwes replied to grai's topic in UVM (Pre-IEEE) Methodology and BCL Forum
hi, either - use the config_db so your sequencer starts the sequence you want - start the sequence manually from the appropriate phase hooks inside new_env - $cast your env to the new_env type if its a new_env, then start the sequence /uwe