qwerty Posted August 27, 2014 Report Share Posted August 27, 2014 Hi, I there a limitation to the number of registers that can be handled by uvm register model? if yes, whats the count. QW Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted August 27, 2014 Report Share Posted August 27, 2014 I don't think there is any hard limitation in place. You just instantiate as many registers as you want. There are no fixed size arrays for the registers to go into. You are, probably, limited by the hardware you're simulating on (i.e. memory), but this has nothing to do with UVM RAL itself. karandeep963 and David Black 2 Quote Link to comment Share on other sites More sharing options...
David Black Posted August 28, 2014 Report Share Posted August 28, 2014 Correct Quote Link to comment Share on other sites More sharing options...
uwes Posted September 8, 2014 Report Share Posted September 8, 2014 hi, there should be no limitations affecting you. there might be simulator limitations (size of arrays etc.) but even those are far away. the typical bounds for the register model are defined by the number of types (registers, registerfiles,...) and instances for compile/elab/simulation. these are soft (=handling) bounds (memory+time) rather then implementation bounds. /uwe karandeep963 1 Quote Link to comment Share on other sites More sharing options...
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