Zdenek Prikryl Posted November 16, 2023 Report Share Posted November 16, 2023 Hello, I have a complex system in SystemC, and I'm using tracing quite a bit. In some cases, the runtime is longer, and the VCD file is quite large, so viewers, such as GTKView, have performance issues with it. On top of that, I'm interested in the last 100 cycles in most cases anyhow. Is it possible to tell the tracer to keep only N cycles in the trace? Any help is appreciated. Thanks. Quote Link to comment Share on other sites More sharing options...
David Black Posted November 16, 2023 Report Share Posted November 16, 2023 Nope; however, some EDA vendors have extended tracing and offer other faster formats for saving the traced data. Hopefully, you are not debugging RTL, since that is better suited for SystemVerilog. You can also speed up things by being very selective in what you trace (i.e., don't trace everything just because you can). Quote Link to comment Share on other sites More sharing options...
Eyck Posted December 3, 2023 Report Share Posted December 3, 2023 You might have a look at the trace file implementations coming with the SCC. Although not having the last N cycles amongst others they allow to delay the start of tracing. Other than that they also provide a implementation to trace into FST so that gtkwave can better handle it. At the last Fika there were some presentations around the topic of tracing: https://systemc.org/events/scef202309/ The second one contains also a few numbers... Quote Link to comment Share on other sites More sharing options...
Zdenek Prikryl Posted December 4, 2023 Author Report Share Posted December 4, 2023 Thank you all. It's not HW debugging per se, but some aspects of the system need to be detailed while others are abstracted. I'm looking for the solution for the case of the detailed parts 🙂 The outcome is that it is not there by default, and some addition is needed (e.g., custom extension). Quote Link to comment Share on other sites More sharing options...
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