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Zdenek Prikryl

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  1. Hello, I have two objects. One is a memory, and the second one is a generator. They are connected via a TLM socket. At the same time, both objects have a method that is sensitive on the clock. The method prepares data for write transactions and it should also pick-up data from reading transactions (and vice versa). It should also check the status of the transactions. I'd like to use a TLM socket for data passing instead of a pin-accurate model of memory interfaces. See the picture in the attachments. The issue is a synchronization because there is a clock (one source of events) and PEQ fo
  2. Hi Alan, This is what I thought. Well, let's do some custom coding then :-).... Thanks.
  3. Hello, I'm trying to develop a memory that supports custom bytes/words. In the usual case, the byte is 8bit and word has 4 bytes (assuming 32bit data-path). Now, in embedded, it's possible that the byte is 12bit and word has 2 bytes (24bit data-path). For 12/24 integers, I can use sc_uint<12> or sc_uint<24>. So, my question is: Is there any helper function that stores/loads a custom int into the generic payload? If not, are there any rules to follow? Thanks.
  4. Hi, Recently I used the following Verilog code in my project: module dff8( input wire CLK, input wire RST, input wire [7:0] D0, output reg [7:0] Q0 ); always @( posedge CLK or negedge RST ) begin if ( RST == 1'b0 ) begin Q0 <= 8'b0; end else begin Q0 <= #10 D0; end end endmodule Is there any way how to model #<DELAY> in SystemC. The example of systemc register that I use is below. SC_MODULE(dff8) { // port declarations sc_in<bool> CLK; sc_in<bool> RST; sc_in<sc_
  5. Hi Alan, Thanks, one more question. LRM page 492 says: In summary, the approach to be taken with the hostendian conversion functions is to write the initiator code as if the endianness of the host computer matched the endianness of the component being modeled, while keeping the bytes within each data word in actual host-endian order. For data words wider than the host machine word length, use an array in host-endian order. Then if host endianness differs from modeled endianness, simply call the hostendian conversion functions. My understanding is that an initiator creates a payload (li
  6. Hi Alan, Following Rahul's post, I have one more question. You mentioned that the interpretation lies in the initiators and targets. So, let's have two initiations (one big, one little) and a bus word has 4 bytes. The target (memory for instance) doesn't allow an unaligned access (address requests have to be: 0, 4, 8, ...). What should the initiations put into payloads when there is a half-word access at an unaligned address? For instance, an initiator wants to write 0xaabb to address 2 (address request goes to 0), Should the data and byte_enable fields of a payload be as follow? Lit
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