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error: no match for 'operator[]' (operand types are 'sc_core::sc_signal<sc_dt::sc_bv<8> >' and 'unsigned int')


acc_sysC
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template <int N> class X : public sc_module

{

public:

sc_signal<sc_bv<2*N> > sY;

sc_vector<sc_signal<sc_bv<1>>> sY_bit{"sY_bit",2*N};

 

X(sc_module_name name) : sc_module(name)

{

SC_METHOD(sY_bit_select);

sensitive << sY  << sY_bit;

 

for(auto G=0U; G< 2*N; ++G)

{

....

....

module1[G].OUT(sY_bit[G]);                        //sc_out<sc_bv<1> > OUT 

}

}

    void sY_bit_select()
    {
        for(auto i=0U; i<2*N; ++i)
        {
            sY[i] = sY_bit[i];     // ERROR
        }

        Y.write(sY);
        
    }

};

In a systemC book I have seen this king of assignment is possible for sc_bv. I'm not sure why its giving this error. Please guide.

 

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No, this is not possible. You are using the array operator for sY_bit which is ok as it is an sc_vector. But on the left hand side you have a signal. A signal has no array operator as it is a single signal.

If you want to assign to a bit position in the bit vector the signal carries you need to read it first, assign and then write since you can only write data of type sc_bv to the signal. So it should look like:

void sY_bit_select() {
   sc_bv<2*N> write_val;
   for(auto i=0U; i<2*N; ++i) {
     write_val[i] = sY_bit[i];
   }
   sY.write(write_val);
} 

 

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@acc_sysC, to help clarify a bit more:

  1. sc_signal<T> is a channel, not data. Conceptually, channels provide transport for data for communication. Use the write() method deposits a copy of the data (as a whole) into the sc_signal channel's write buffer (next_value). At the end of the delta cycle, the write buffer is copied into the current_value in it's entirety. The read() method simply returns a copy of the current_value.
  2. sc_bv is a data type, not a channel, and supports bit-specific access (reading and writing) via operator[].
  3. Finally, if you use ports (e.g., sc_in<T> or sc_out<T>, which are really just specializations of sc_port<sc_signal_in_if<T>> and sc_port<sc_signal_inout_if<T>> respectively), they are effectively pointers to channels that support the channel's API's.

I mention this because newbies to SystemC frequently confuse the ideas of data, channels, and ports.

Finally, before you ask: No, there is unlikely to be any attempt to "fix" SystemC to provide extensions to all of this to make modeling at this (low-level) more comfortable. SystemC attempts to raise the abstraction level and tends to avoid bit/pin twiddling. If you need to code RTL, please use SystemVerilog or VHDL.

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@Eyck I tried this. I am still getting the error.

error: no match for 'operator=' (operand types are 'sc_dt::sc_bitref<sc_dt::sc_bv_base>' and 'sc_core::sc_vector<sc_core::sc_signal<sc_dt::sc_bv<1> > >::element_type {aka sc_core::sc_signal<sc_dt::sc_bv<1> >}')
             write_val[i] = sY_bit[i];

 

I have done a similar thing in another module. It worked fine. I'm not sure what went wrong.

Here's the EDA link https://www.edaplayground.com/x/X3WN

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