error: no match for 'operator[]' (operand types are 'sc_core::sc_signal<sc_dt::sc_bv<8> >' and 'unsigned int')

[acc_sysC]

template <int N> class X : public sc_module

{

public:

sc_signal<sc_bv<2*N> > sY;

sc_vector<sc_signal<sc_bv<1>>> sY_bit{"sY_bit",2*N};

 

X(sc_module_name name) : sc_module(name)

{

SC_METHOD(sY_bit_select);

sensitive << sY  << sY_bit;

 

for(auto G=0U; G< 2*N; ++G)

{

....

....

module1[G].OUT(sY_bit[G]);                        //sc_out<sc_bv<1> > OUT 

}

}

    void sY_bit_select()
    {
        for(auto i=0U; i<2*N; ++i)
        {
            sY[i] = sY_bit[i];     // ERROR
        }

        Y.write(sY);
        
    }

};

In a systemC book I have seen this king of assignment is possible for sc_bv. I'm not sure why its giving this error. Please guide.

 

[Eyck]

No, this is not possible. You are using the array operator for sY_bit which is ok as it is an sc_vector. But on the left hand side you have a signal. A signal has no array operator as it is a single signal.

If you want to assign to a bit position in the bit vector the signal carries you need to read it first, assign and then write since you can only write data of type sc_bv to the signal. So it should look like:

void sY_bit_select() {
   sc_bv<2*N> write_val;
   for(auto i=0U; i<2*N; ++i) {
     write_val[i] = sY_bit[i];
   }
   sY.write(write_val);
} 

 

[David Black]

@acc_sysC, to help clarify a bit more:

1. sc_signal<T> is a channel, not data. Conceptually, channels provide transport for data for communication. Use the write() method deposits a copy of the data (as a whole) into the sc_signal channel's write buffer (next_value). At the end of the delta cycle, the write buffer is copied into the current_value in it's entirety. The read() method simply returns a copy of the current_value.
2. sc_bv is a data type, not a channel, and supports bit-specific access (reading and writing) via operator[].
3. Finally, if you use ports (e.g., sc_in<T> or sc_out<T>, which are really just specializations of sc_port<sc_signal_in_if<T>> and sc_port<sc_signal_inout_if<T>> respectively), they are effectively pointers to channels that support the channel's API's.

I mention this because newbies to SystemC frequently confuse the ideas of data, channels, and ports.

Finally, before you ask: No, there is unlikely to be any attempt to "fix" SystemC to provide extensions to all of this to make modeling at this (low-level) more comfortable. SystemC attempts to raise the abstraction level and tends to avoid bit/pin twiddling. If you need to code RTL, please use SystemVerilog or VHDL.

[acc_sysC]

@Eyck I tried this. I am still getting the error.

error: no match for 'operator=' (operand types are 'sc_dt::sc_bitref<sc_dt::sc_bv_base>' and 'sc_core::sc_vector<sc_core::sc_signal<sc_dt::sc_bv<1> > >::element_type {aka sc_core::sc_signal<sc_dt::sc_bv<1> >}')
             write_val[i] = sY_bit[i];

 

I have done a similar thing in another module. It worked fine. I'm not sure what went wrong.

 

[acc_sysC]

@David Black Thanks for the heads up! These are very useful points for a newbie like me.

[Eyck]

Seems the compiler cannot infer the read function. SO the example would look like
 

void sY_bit_select() {
   sc_bv<2*N> write_val;
   for(auto i=0U; i<2*N; ++i) {
     write_val[i] = sY_bit[i].read();
   }
   sY.write(write_val);
} 

Actually I personally prefer to use the explicit read() and write() functions instead of the overloads. Those work in many case but -as you encounted- not all.

[acc_sysC]

@Eyck I tried using sY_bit[i].read() too. It did not make any difference.

 

Could this be because of using sc_bv in most of the places? I thought of changing everything to sc_uint or sc_biguint. Do you think that will work?

 

Also, is this the right way to concatenate?

    void concat_method_sY()
    {
        sc_bv<2*N> s;
        sc_bv<4> first_nib;
        sc_bv<4> sec_nib;

        s = sY;
        first_nib = s.range(3,0);
        sec_nib = s.range(7,4);

        sY_A = (first_nib,A);
      
        sY_B = (sec_nib,B);

    }

[David Black]

I concur with @Eyck on the use of explicit read/write. Using the operator= override can lead to unexpected interpretation, and the explicit presence of method calls alerts the reader to the presence of a channel behavior.

If you care about simulation performance, I would avoid sc_biguint and sc_uint if possible. Native C++ types work great and are much faster. Many models are written without using the SystemC datatypes at all. Some groups even forbid them except at the interface points to SystemVerilog or VHDL for this reason. Bit twiddling is a simple art. For really large vectors, sc_bv is fine, but you might also consider std::vector<bool> and std::bitset<N>. [See https://stackoverflow.com/questions/4156538/how-can-stdbitset-be-faster-than-stdvectorbool for a comparative comment.]

[acc_sysC]

@David Black Thanks I'll try using read/write instead of operator=

[acc_sysC]

I used your suggestions and was able to rectify errors so it complies now.

But when I execute it, I get this error:

Error: (E100) port specified outside of module: port 'port_0' (sc_port_base)
In file: ../../../src/sysc/communication/sc_port.cpp:235
Exit code expected: 0, received: 1

How do I find where the error is? I'm not able to move forward without understanding this error. Please guide me.

 

[acc_sysC]

I found it. Named the ports in all the modules and I could track it.

[acc_sysC]

How do I track this error? like line number of the error  etc

Error: (E202) cannot perform conversion: string can contain only '0' and '1' characters