Error: (E529) insert module failed: simulation running

[acc_sysC]

Hi all! I'm new to systemC. I'm trying to instantiate a register module multiple times in another module. Both of which are parameterized. Can someone tell me why I get the following error:

Error: (E529) insert module failed: simulation running
In file: ../../../../src/sysc/kernel/sc_module_registry.cpp:47
In process: REG_FILE.prc_register_file @ 0 s

These are my modules in systemC:

//INSTANTIATED MODULE

class register256 : public sc_module {
public:
    sc_in<sc_bv<256> > DATA_IN;
    sc_in<bool> WRITE;
    sc_in_clk clk;
    sc_in<bool> reset;
    sc_out<sc_bv<256> > DATA_OUT;
    sc_bv<256> DATA;

    SC_HAS_PROCESS(register256);
    register256(sc_module_name name) : sc_module(name) //constructor that takes paprameter
    {
        SC_METHOD(prc_register256);
        sensitive << clk << reset;

    }

    void prc_register256 ()
    {
        if(reset)
            DATA = 0;
        else if(WRITE)
            DATA = DATA_IN;
        DATA_OUT = DATA;

        cout<< "at time: " << sc_time_stamp()<< endl << "DATA_OUT = "<< DATA_OUT.read() <<endl;
        cout<< "at time: " << sc_time_stamp()<< endl << "DATA_IN = "<< DATA_IN.read() <<endl;
    }

};

//INSTANTIATING MODULE

template <unsigned N, unsigned M> class register_file : public sc_module
{
public:

    // int K = 0;
    // K = M*N;
    sc_in<sc_bv<N> > DATA_IN;
    sc_in<sc_bv<M> > WRITE_ADDR;
    sc_in<bool> WRITE_EN;
    sc_in<bool> READ_EN;
    sc_in_clk clk;
    sc_in <bool> reset;
    sc_out<sc_bv<256> > DATA_OUT; 

    SC_HAS_PROCESS(register_file);

    register_file(sc_module_name name): sc_module(name)
    {
        SC_METHOD(prc_register_file);
    }

        int G;

    //Generate statement
    void prc_register_file()
    {
    

        int UPPER_LIMIT;
        int LOWER_LIMIT;
        sc_bv<256> data_out;
        char buf[10];

        for (G=0; G<M; G++)
        {

            sprintf(buf, "r%d", G);
            register256<N> *registers;
            registers = new register256<N> (buf);
            registers-> DATA_IN(DATA_IN);
            if(WRITE_ADDR[G])
            registers->WRITE(WRITE_EN);

            registers->clk(clk);
            registers->reset(reset);
            UPPER_LIMIT = (N*(G+1))-1;
            LOWER_LIMIT = N*G;
            data_out = DATA_OUT.read();
            data_out = data_out.range(UPPER_LIMIT,LOWER_LIMIT);
            DATA_OUT = ( sc_bv<256> ) data_out; //ALWAYS 255
            registers->DATA_OUT(DATA_OUT);

            cout<< "at time: " << sc_time_stamp()<< endl << "DATA_OUT = "<< DATA_OUT.read() <<endl;
            cout<< "at time: " << sc_time_stamp()<< endl << "DATA_IN = "<< DATA_IN.read() <<endl;

        }

        //Destructor

        // ~register_file()
        // {

        //     delete[] registers;
        
        // }

    }

};

 

 

int sc_main(int argc, char* argv[]) {

    sc_signal<sc_bv<256> > DATA_IN;
    sc_signal<sc_bv<8> > WRITE_ADDR;
    sc_signal<bool> WRITE_EN;
    sc_signal<bool> READ_EN;
    //sc_in_clk clk;

    sc_clock clk("c1", 1, SC_NS);
    sc_signal<bool> reset;
    sc_signal<sc_bv<256> > DATA_OUT;

    
    //create instance
    register_file<256,8> rf("REG_FILE");
    //register_file rf("rf1", N);
    rf.DATA_IN ( DATA_IN );
    rf.WRITE_ADDR ( WRITE_ADDR );
    rf.WRITE_EN ( WRITE_EN );
    rf.READ_EN ( READ_EN );
    rf.clk ( clk );
    rf.reset ( reset );
    rf.DATA_OUT ( DATA_OUT );

    stimulus<256> stim1("stim1");
    stim1.Data_in(DATA_IN);
    stim1.write_addr(WRITE_ADDR);
    stim1.write_en(WRITE_EN);
    stim1.read_en(READ_EN);
    stim1.reset(reset);

    //invoke the simulator

    sc_start(10,SC_NS);
    return 0;

}

 

[David Black]

Please place your code on EDAplayground.com and provide a link once you get it to compile.

 

[maehne]

You cannot instantiate modules in an SC_METHOD, as it will only execute during simulation. You have to do the instantiation in the constructor, so that it is done during elaboration. Also, multiple instances of a module are best instantiated using an sc_vector as container.

[acc_sysC]

@David Black Here's the link to EDAplayground with the code https://www.edaplayground.com/x/YJuW. It does not compile though. I have questions on that.

To perform WRITE_EN and write_addr[G], do I need to save it to another dummy variable and then connect it? 

or directly use regs.WRITE(WRITE_EN and write_addr[G]); ?

Either ways I get errors. Mostly data type conflicts. Can you please guide?

 

 

 

[acc_sysC]

@maehne I tried to use SC_HAS_PROCESS instead. Still facing a lot of issues with the instantiation. Please guide me.

[Eyck]

Your code lacks a basic understaning of the lifetime of (C++) variables and the use of signals. The following poblems exist In the constructor of register_file:

• line 45: you instantiate regsiter256 as local variable. This will be deleted as soon as the for loop is left.
• line 47: you describe behavior, but you can only instantiate and wire modules, ports and alike. This has to be moved to a separate SC_METHOD being decalred in the constructor
• line 56: You conect plain C++ type to port. Ports can only be connected to signals or other ports.

I took your code and changed it in a way that it builds and runs - no guarantee that it is correct. You may find it at https://www.edaplayground.com/x/C8is

[acc_sysC]

@Eyck Thank you for your reply. I'm able to see some output now although not correct. I will work on it.

Is there any reason for performing the && operation in the register256 module instead of register_file?

I want to perform the && operation in register_file and then send it to register256. That was it will not change the architecture of my modules. But I was not able to do this.

[David Black]

On 5/30/2022 at 7:04 AM, Eyck said:

• line 56: You conect plain C++ type to port. Ports can only be connected to signals or other ports.

I would amend that statement to read: 

• line 56: ... Ports can only be connected to channels, or ports (if navigating up the design hierarchy) or sc_export's. Not that ports such as sc_in and sc_out are really just template specializations of sc_port<INTERFACE>, where INTERFACE is either sc_signal_in_if<TYPE> or sc_signal_inout_if<TYPE>.