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Everything posted by petermonsson

  1. Hi Santosh, You need to add a new address map to your register model. See the user guide section 5.5.5 and section Best Regards Peter
  2. Hi, We have a configuration class per environment and an environment for each logical block that we want to verify. The top-level configuration object hierarchy matches the environment hierarchy. I think that your approach is solid. Best Regards Peter
  3. Hi, We have relatively few sequences. I don't know why. It just seems like we never need that many. Most tests are also pretty small so we keep them in functional/logical groups in a file per group. Often there will be a base test from which the other tests in the library inherit from. Best Regards Peter
  4. Hi Ryan, I don't see why the virtual sequence doesn't work. What do you mean with the fields get populated? What kind of side effects would something like this have? rand bit [2:0] m_rand_sqr; task body(); seq = my_seq::type_id::create("seq"); seq.start(p_sequencer.my_sqr[m_rand_sqr]); endtask Best Regards Peter
  5. Hi Peer, I think that you will want to use an array of queues: monitor_trans exp_trans_port[][$]; (or monitor_trans exp_trans_port[$][]; I don't recall the correct order) exp_trans_port = new[num_trans_ports]; Best Regards Peter
  6. Hi David, Sorry for the late reply (holidays and all that). In your create_map call you specify "word addressing" (the last parameter). The documentation states: "byte_addressing specifies whether consecutive addresses refer are 1 byte apart (TRUE) or n_bytes apart (FALSE). Default is TRUE." In other words, you tell create_map that you want consecutive locations to be addressed with +1. If you set byte_addressing = 1, things should be OK. Let me know if it works. Peter
  7. Hi David, What do the create_map() lines look like? Best Regards Peter
  8. Hi, The uvm_in_order_comparator is pretty old and inflexible. I am afraid that there is no easy way for you to do what you want. I create a predictor (uvm_subscriber) on one or both sides of the in order comparator and "zero out" the fields that I don't want to be compared. Best Regards Peter
  9. Hi Peer Mohammed , I don't remember which version that I have, but I don't remember having this problem. Do you have the latest release/patches from your vendor? I think that the single line comment is legal per the SystemVerilog LRM. Best Regards Peter
  10. Hi Phil, I would drop out of the register layer and just run a burst sequence on the bus directly. If the registers are on an AXI bus, then I would run an AXI sequence with burst directly. Best Regards Peter
  11. I think the short answer is malware. The forum has had problems in the past.
  12. Hi all, My simulator has a profile switch so I profile my code. I don't recognize the problems mentioned with macros. I have never seen a problem with their performance. I am curious. Where do you typically experience problems? Best Regards Peter
  13. I recommend that you use peek() for checking the write operation. If you are using a built in register sequence which fails, then let me know. I will file a bug report.
  14. I don't know what UVM_WZ is and the internet is no help either. I recommend that you use the newest UVM version (which at this time is version 1.1c)
  15. Hi Sylvain, My functional coverage skills aren't that great. Covergroups can give you some flexibility which I haven't used in the example test bench. See for example section 20.4 in the SystemVerilog 3.1a standard. Maybe you can make something work. Best Regards Peter
  16. Hi, In my opinion it is easiest to use a uvm_subscriber which is connected to the analysis port of the monitor. SystemVerilog has lots of limitations when it comes to inheritance and covergroups. You can have a look at an example of a coverage subscriber in cov_test_lib.sv in "Linear PCM integrated example test bench" in the UVM Contributions section. Best Regards Peter
  17. Hi Ryan, I think that you're on the right track. I don't have anything better. Best Regards Peter
  18. Hi, I am afraid not. Ask your simulator vendor whether they have something similar. Best Regards Peter
  19. Hi Sandip, You can have multiple register models in your environment. Often life is easier if you create a wrapper uvm_reg_block around the many generated blocks that you have. Best Regards Peter
  20. Hi, A function requires you to not use any simulation time. A task does not. This doesn't mean that a task has to use simulation time. You can make your task complete in zero time, no problem. Best Regards Peter
  21. Hi, I've reported the bug for you: http://www.eda.org/svdb/view.php?id=4363 Best Regards Peter
  22. Hi Adrian, I've reported the bug for you: http://www.eda.org/svdb/view.php?id=4362 Best Regards Peter
  23. Hi, model is defined in uvm_reg_sequence: http://www.vmmcentral.org/uvm_vmm_ik/files3/reg/uvm_reg_sequence-svh.html#uvm_reg_sequence.model reg_dut regmodel is defined in reg_model.svh in examples/integrated/codec Best Regards Peter
  24. Hi, I am afraid that we can't help you with the information that you have provided. Here is an idea: You have a deadlock inside your virtual sequence that goes through a non-virtual sequence, a driver, the analysis fifo, the virtual sequencer and back to the virtual sequence. It is a long shot. I hope this helps. Peter
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