Shashank V M Posted June 24, 2021 Report Share Posted June 24, 2021 I am trying to model an OR gate with 2 NS output delay in SystemC. #include "systemc.h" SC_MODULE(adder) { sc_in<bool> A, B; sc_out<bool> OUT; void add() { while (true){ wait(A.default_event() | B.default_event()); bool intermediate = A.read() | B.read(); wait(2, SC_NS); //cout << "adding at time " << sc_time_stamp() << endl; OUT.write(intermediate); } } SC_CTOR(adder){ SC_THREAD(add); sensitive<< A << B;; } }; This is my attempt so far. But the simulation result is not as required: Time A B OUT 0 s 0 0 0 5 ns 1 0 0 6 ns 0 0 0 7 ns 0 0 1 13 ns 0 1 1 Instead of being 0 at 8 NS, it has missed the event at 6 NS. In Verilog, the events is similarly missed if blocking assignment is used. In Verilog, we fix it using non-blocking assignment (See this about Verilog: https://electronics.stackexchange.com/q/572643/238188). So how do I stop the event from getting missed in SystemC? Quote Link to comment Share on other sites More sharing options...
AmeyaVS Posted June 24, 2021 Report Share Posted June 24, 2021 Hello @Shashank V M, That's why you need to use a non-blocking process SC_METHOD to model such behavior. You can find relevant discussion here: Quote Hope it helps. Regards, Ameya Vikram Singh Shashank V M 1 Quote Link to comment Share on other sites More sharing options...
David Black Posted June 24, 2021 Report Share Posted June 24, 2021 You could use: #define SC_INCLUDE_DYNAMIC_PROCESSES #include <systemc> //... sc_signal<int, SC_MANY_WRITERS> sig; //... sc_spawn( [&](){ wait(DELAY); sig.write(VALUE); } ); See https://www.edaplayground.com/x/WjWw for an example. Shashank V M 1 Quote Link to comment Share on other sites More sharing options...
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.