kurtlin

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VCS 2019.06 strong and weak support

kurtlin replied to ljepson74's topic in UVM Simulator Specific Issues

How about replace the switch from "-sverilog" to "-sv=2009"?
- August 25, 2020
- 4 replies
Venkatesh reacted to a post in a topic: ERROR IN NCSIM Simulation -E,CUVMUR April 25, 2017
ERROR IN NCSIM Simulation -E,CUVMUR

kurtlin replied to Venkatesh's topic in UVM Simulator Specific Issues

Hi Venkatesh, You can check the details of this message via this command: nchelp ncelab CUVMUR I think you did not compile rcd2_top befor gen_ddr4_rcd_chip in your environment. Thanks, Kurt
- April 22, 2017
- 1 reply
- - 1
UVM Compliance Checklist

kurtlin reviewed sharonr's file in UVM
- November 30, 2016
Don't care bit handling in UVM RAL

kurtlin posted a topic in UVM SystemVerilog Discussions

Not sure do you have similar problem? I have a problem in handling the reset value in RAL. f the reset value of a field in the register is don't care, what can I do for it? Now my plan is extend a new access type. For this kind of registers, the read value in reset test is not checked. Do you guys think it is a feasible way? Thanks.
- August 20, 2013
- - uvm
  - ral
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