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Hi All,

I am looking to model SRAM (SC_MODULE (memory) ) which has n Rd and m Wr ports. It has multiple banks. Transaction from ports need to be arbitrated for bank conflicts. 

1. What is best way to model multiple ports ? Would it be clean to use list / vector of simple_target_socket_tagged <> ? 

2. Would having a 'router' between (n+m) ports and banks make for cleaner class design ?

3. If we take up simple port based design as opposed to using a router - what would be best way to manage 4 phase socket communication protocol ? 

3. Do we need to pay attention to how storage is modelled ? For example - would having a simple array based storage be faster vs std::map based storage ?

4. Ideally, would like the port data bitwidth and SRAM bank bitwidths to be same as configurable via template. 

Thanks

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  1. Use either the multi_passthrough_target_socket<T> or any of the tagged sockets
  2. Not necessary
  3. You probably would need to use std::vector to manage various protocol related state variables per port. Obviously use the payload command field to distinguish Read/Write.
  4. Simple arrays are definitely faster and allow for DMI
  5. Sockets have built-in width already. Since width is generally a multiple of 8 bits, I would probably factor that into an aspect of my arrays.
  6. Take a look at Boost library for multi-dimensional arrays that would have decent performance for the memory since it will likely be multi-dimensional.
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Thanks for your response and help David.I was particularly indecisive about #2. 

I am designing solution along lines of your suggestion in #3. Will design a 'MemPort' class which implement 4 phase base protocol using simple_target_socket_tagged<>, and array of n such port objects will be instantiated in parent class called 'Memory'. Thus every port's socket would invoke 'arbiter' (a member function in parent Memory class ), upon receiving a Tx at the port (as response to BEGIN_REQ phase).

Question 7 : The arbiter decides the priority of Tx based on Port ID. So Tx from 0, 1, 2 ..., n will be prioritized in decreasing order of priority. Thus if two ports, lets say Port 0 and port 1 - gives Tx at the same time - then 0's Tx need to be prioritized higher. How can I make sure that 'arbiter' is called first by port 0 and not port 1 (when the Tx at both port arrives at same time) ?

Question 8 : My 'Memory' class which uses n ports (each with 4 phase base protocol communication sockets) - is part of a larger ComputeEngine model. The compute is dominated by data transfers to/from memory. My very top level, and subjective  question is - will my ComputeEngine model be accurate to be with 5% of RTL/Verilog design in terms of cycles / time reported for a given workload (running on RTL simulator and my ComputeEngine model) ?

Thanks

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