iamgame Posted June 16, 2020 Report Share Posted June 16, 2020 Hi All, I am looking to model SRAM (SC_MODULE (memory) ) which has n Rd and m Wr ports. It has multiple banks. Transaction from ports need to be arbitrated for bank conflicts. 1. What is best way to model multiple ports ? Would it be clean to use list / vector of simple_target_socket_tagged <> ? 2. Would having a 'router' between (n+m) ports and banks make for cleaner class design ? 3. If we take up simple port based design as opposed to using a router - what would be best way to manage 4 phase socket communication protocol ? 3. Do we need to pay attention to how storage is modelled ? For example - would having a simple array based storage be faster vs std::map based storage ? 4. Ideally, would like the port data bitwidth and SRAM bank bitwidths to be same as configurable via template. Thanks Quote Link to comment Share on other sites More sharing options...
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