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iamgame

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Everything posted by iamgame

  1. Hi Eyck and David, Thanks for your responses and help. David - we do have situations where target's (t1) response beats (to a burst req from initiator I1) would be interleaved with response beats from initiator I2. I.e. intra-burst interleaving is required in our model. Could there be ways of 'accounting for' additional delays due to intra-burst interleaving on target's side ? For example - Target T1 has two ports (sockets, 16 bit BUSWIDTH), P1 and P2. On each port T1 gets a req of 64 bits read (resulting in 4 beat response on each port) , and would likely send out data in this seq - BEGIN_RESP_P1_Beat1, BEGIN_RESP_P2_Beat1, BEGIN_RESP_P1_Beat2, BEGIN_RESP_P2_Beat2 ... In such scenario - extending your idea of 'target setting the latency' - can we double the latency for each port ? Interleaving mainly happens due to bank conflict / arbitration. Thanks.
  2. Hi All, We are using convenience sockets (simple initiator/target) in our project, with few point to point buses and simple interconnects and nb_transport() (using 4 Ph base protocol). What would be best way of handling Tx which are longer in length than BUSWIDTH. 4 phase base protocol does not provide 'intermediate' states to let us break transactions into multiple beats. I was unable to glean from SystemC or TLM examples. Could we modify 4 ph protocol to add additional states (for a write Tx) like BEGIN_REQ, BEGIN_NEW_DATA, .(repeat this states as many times as needed; data would be transferred in this state) .., BEGIN_LAST_DATA (to indicate this is last beat). Similarly there would be new states for read Tx. BEGIN_RESP_NEW_DATA, (repeat) and BEGIN_RESP_LAST_DATA. Does this sound complicated ? Thanks.
  3. Hi David, My apologies in getting late about expressing thanks/gratitude for your help. Thank you. Thanks.
  4. 1. Cluster – Is a module, which hosts various compute elements, and multiple arrays of DMEs. In this block diagram two DME-Array – each comprising of 4 DMEs is shown. Cluster is connected to multiple NoCs. Each DME-Array is connected to a NoC based on memory type that the array hosts. 2. DME – Dma and memory element. One DME differs from another in terms of size/banks, security and power characteristics (voltage, and power states) of its memory. There are specific NoC to connect DME-Arrays with specific mem type. There could be multiple NoCs, each connecting common MemType DM arrays. Two such NoCs are shown. 3. DME-Arrays would exchange data with DME-Arrays of another cluster over Noc. We want to model this using convenience sockets. All Transactions originating or terminating from a DME of an DME-Array, would be arbitrated using simple round robin method, and sent to NoC using simple_initiator_socket shown as green bubble. Tx is received in DME-Array from NoC using simple_target_socket using yellow bubble. 4. We want only a pair of initiator / target socket serving all elements of a DME-Array. We would like to instantiate these sockets inside DME class – but have it as static member of the DME-class. This is prohibited by design of the convenience sockets. For now we have instantiated the sockets in Cluster class which is parent of DME. This clutters Cluster class – as these sockets are not used by Cluster class directly or indirectly. They are there because DME would use/access them via parent pointer.
  5. Hi David, Please find the block diagram attached. The textual description that goes with the pic, is in subsequent message. Thanks.
  6. Hi David, Thanks for your response. I will draw a pic and try to highlight the need. Apologize the delay. Thanks.
  7. Hi David, Thanks for you time and response. 1. If I use initializer list of constructor, I would be initializing the socket (a static variable) multiple times. I am looking to design the code in such a way that multiple instances of my_module will all same same socket to send/receive their request. 2. I do not understand uniform initialization syntax. After I declare static tlm_utils::simple_target_socket<my_module> socket; in the definition of class my_module and define the static variable in my source file as tlm_utils::simple_target_socket<my_module> my_module::socket_; I tried initializing it (conditionally, in the constructor) as - socket_ = tlm_utils::simple_target_socket<my_module>("socket") But this run into compiler error as, the socket's assignment operator is disabled/not-allowed. Thanks.
  8. Hi All, Is it possible to have simple_target_socket as static member of a module ? It needs to defined outside the class, can we define and initialize it in constructor ? // header class my_module : public sc_core::sc_module { public: my_module(sc_module_name name); static bool isSockettInitialized_; static tlm_utils::simple_target_socket<my_module> socket_; }; // source file //instantiate socket, cannot initialize it, because it is outside sc_module - it would throw and E100 error. tlm_utils::simple_target_socket<my_module> my_module::socket_; bool my_module::isSockettInitialized_ = false; my_module::my_module(sc_module_name name) : sc_module(name) { if (!isSocketInitialized){ isSocketInitialized = true; // would like to initialize socket_, here, but tlm_utils::simple_target_socket<> class disables assignment operator } } I am unable to find a way to initialize the socket_. 1. If I initialize it outside constructor - I get the error - "Error: (E100) port specified outside of module:" 2. Do not know how to initialize in constructor (as the assignment is disabled) Please help.
  9. Hi All, I coded up (in TLM) few modules for my SoC (cache mem, interconnects, dma engines etc). I have mostly used simple_initiator_socket and simple_target_sockets for all of my SoC components. I'm modelling for cycle accurate comparison with RTL. My aim is to correlate model with RTL design - in terms of cycles consumed, peak/avg bandwidth/latencies at internal and external memories. What is best way to extract, log and aggregate this information ? Is accumulating delays and time info across API calls like simple_initiator_socket::nb_transport_fw/bw() best way to do it ? Are there TLM APIs which aggregates such information over life cycle of simulation run ? After we get all the info rolled up into final numbers, what metrics (e.g. avg cycle / mem req) are typically compared between TLM and RTL design ? Are there some open source designs where model and design are compared ? Thanks
  10. Thanks Eyck. I guess I forgot to add important detail. Class ExistingDesignBase as mentioned in first version - is base for every module in design. There are about 40 modules in the design. And the top level class TlmModule, has few modules inside it. Could this lead up to any issue to sc_module hierarchy ? I observed that this message is thrown from sc_port.cpp if the check for parent of sc_module fails. Thanks
  11. Hi All, I am modifying an existing functional model for my hardware to make it cycle accurate. I get aforesaid error, for my slightly longer hierarchy of classes. class Port { tlm_utils::simple_target_socket<Port> socket_; } class Memory { Port *port; } class TlmMemory::public ExistingMemory{ Memory *mem; } class TlmModule :: public ExistingModule { TlmModule(sc_module_name nm); //socket connection is done here. tlm_utils::simple_initiator_socket<TlmModule> socket_; TlmMemory *tlmMem; } class ExistingModule :: public ExistingModuleBase { } class ExistingModuleBase :: public ExistingDesignBase { } class ExistingDesignBase :: public sc_core::sc_module { } However I do not get the error with following, however this is not what I would ideally like to do - class TlmModule :: public ExistingModule, public sc_core::sc_module { TlmModule(sc_module_name nm); //socket connection is done here. tlm_utils::simple_initiator_socket<TlmModule> socket_; TlmMemory *tlmMem; } class ExistingModule :: public ExistingModuleBase { } class ExistingModuleBase :: public ExistingDesignBase { } class ExistingDesignBase { } I would like request help about why my first method of putting sc_module at the bottom of my class hierarchy is not working. Thanks.
  12. Dear TLM Experts, Could someone please shed some light on this ? I have been able to create a transactionID using extension in GP. In order to trace how each transaction is progressing in my system, I am thinking of using transport_dbg API of sockets, such that every time a socket sends or receives a Tx - it will get logged. Would this be right / clean way of logging every Tx ? I am not clear yet about who would call transport_dbg (with in socket class) after I register a callback for transport_dbg ? Also when is transport_dbg called when Tx travels via non blocking interfaces of an initiator or target sockets ? Thanks.
  13. Hi All Basically for debugging purpose I want to trace every transaction (Tx) going around in my model. I would like to assign an ID to each Tx so that it becomes easy to trace them. I have following questions in this context. I am in early stages of using TLM . 1. What is best way to annotate each Tx ? a) I am thinking of using extensions in generic payload - following ./tlm-2/examples/lock_example.cpp b) Could there be some generic TLM classes in open source that people developed for this specific purpose ? I am thinking of wrappers around core gp, and enhanced sockets classes which could facilitate monitoring and logging of Tx using IDs. 2. What is best way to switch between debug and release version - wherein debug version each Tx is traced ? I guess, like 1.b, I am again asking if you know of open source wrapper classes which can facilitate this in run time ? Thanks.
  14. Hi SC/TLM experts, I have same question/need. Could someone please enlighten ? Are there examples which illustrates usage of gp extensions ? Thanks.
  15. Hi Eyck, Thanks for your replay and help. Will reach out. Thanks.
  16. Hi Folks, Are there good open source libraries out there to model (AT/FT style) SoC components (memories, buses, simple nocs, dma engines, registers which can be decoded off of APB) ? Upon some searching I came across - 1. scml/scml2 - https://gitlab.larc-nthu.net/rgly/scml/-/tree/6cb6356704245b9c17f816ba957f1a0971d76a67 (does not offer bus components) 2. System C components - https://github.com/Minres/SystemC-Components (offers bus components - but the buses do not seem to have non block transfer interface) 3. VCML - https://github.com/janweinstock/vcml (offers bus components - but the buses do not seem to have non block transfer interface) Any recommendations ? I am particularly interested in bus models (ring architecture, simple noc and bus with protocols like OCP, APB) and registers which are addressed over APB bus. Thanks.
  17. Thanks for your response and help David.I was particularly indecisive about #2. I am designing solution along lines of your suggestion in #3. Will design a 'MemPort' class which implement 4 phase base protocol using simple_target_socket_tagged<>, and array of n such port objects will be instantiated in parent class called 'Memory'. Thus every port's socket would invoke 'arbiter' (a member function in parent Memory class ), upon receiving a Tx at the port (as response to BEGIN_REQ phase). Question 7 : The arbiter decides the priority of Tx based on Port ID. So Tx from 0, 1, 2 ..., n will be prioritized in decreasing order of priority. Thus if two ports, lets say Port 0 and port 1 - gives Tx at the same time - then 0's Tx need to be prioritized higher. How can I make sure that 'arbiter' is called first by port 0 and not port 1 (when the Tx at both port arrives at same time) ? Question 8 : My 'Memory' class which uses n ports (each with 4 phase base protocol communication sockets) - is part of a larger ComputeEngine model. The compute is dominated by data transfers to/from memory. My very top level, and subjective question is - will my ComputeEngine model be accurate to be with 5% of RTL/Verilog design in terms of cycles / time reported for a given workload (running on RTL simulator and my ComputeEngine model) ? Thanks
  18. Hi All, I am looking to model SRAM (SC_MODULE (memory) ) which has n Rd and m Wr ports. It has multiple banks. Transaction from ports need to be arbitrated for bank conflicts. 1. What is best way to model multiple ports ? Would it be clean to use list / vector of simple_target_socket_tagged <> ? 2. Would having a 'router' between (n+m) ports and banks make for cleaner class design ? 3. If we take up simple port based design as opposed to using a router - what would be best way to manage 4 phase socket communication protocol ? 3. Do we need to pay attention to how storage is modelled ? For example - would having a simple array based storage be faster vs std::map based storage ? 4. Ideally, would like the port data bitwidth and SRAM bank bitwidths to be same as configurable via template. Thanks
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