Bes Posted April 7, 2020 Report Share Posted April 7, 2020 Can someone help how could do something like this using systemc Quote Link to comment Share on other sites More sharing options...
David Black Posted April 7, 2020 Report Share Posted April 7, 2020 This looks like homework and a trivial FSM. Most of the coding would be simple C++. Good luck! Bes 1 Quote Link to comment Share on other sites More sharing options...
Bes Posted April 7, 2020 Author Report Share Posted April 7, 2020 I’m kinda confused with the syntax for systemc, I don’t know if the states or the keys are input ports or just signals not with the fsm logic Quote Link to comment Share on other sites More sharing options...
David Black Posted April 7, 2020 Report Share Posted April 7, 2020 Depends on what the problem statement is. Likely as not, the test will rely on some type of SystemC ports for the inputs. Quote Link to comment Share on other sites More sharing options...
hbhbts Posted April 22, 2020 Report Share Posted April 22, 2020 SC_MODULE(Fsm) { sc_in<bool> clk; sc_in<bool> reset; sc_in<bool> is_valid; sc_in<bool> is_half_dollar; sc_out<bool> is_dispensed; SC_CTOR(Fsm) { SC_THREAD(fsm_thread); sensitive << clk.pos(); }; void fsm_thread() { typedef enum {S0=0, S1=1, S2=2, S3=3} state_e; state_e state = S0; while(true) { is_dispensed.write(false); if(reset.read() == false) { switch(state) { case S0: if(is_valid.read() == true && is_half_dollar.read() == true) state = S1; else state = S2; break; case S1: if(is_valid.read() == true && is_half_dollar.read() == true) state = S2; else state = S3; break; case S2: if(is_valid.read() == true) state = S3; break; case S3: is_dispensed.write(true); state = S0; break; default: state = S0; } } else state = S0; wait(); } }//fsm_thread }; Bes 1 Quote Link to comment Share on other sites More sharing options...
Bes Posted April 26, 2020 Author Report Share Posted April 26, 2020 Thank youu Quote Link to comment Share on other sites More sharing options...
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