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sc_fifo module hierarchy (connecting FIFO between 2 modules running in different clock threads)


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      I am trying to connect a custom fifo between 2 modules, that works fine in simulation and verification in my linux and also vivado hls but when i try to synthesize it using vivado hls , it give an error as,  

ERROR: [SYNCHK 200-91] Port 'imp.cons.in.m_if.Val.data' (../final/p.h:200) of function 'center_detector' cannot be set to a FIFO 
ERROR: [SYNCHK 200-91] as it has both write (../final/x.h:19:17) and read (../final/y.cpp:9:4) operations.

Is that synthesizable or not ?

 sc_port<sc_fifo_out_if<line> >out; // producer module port

sc_port<sc_fifo_in_if<line> > in; // consumer module port


my read and write operations as



I saw this similar topic in https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/SystemC-sc-fifo-and-hierarchy/td-p/741511 , but i couldn't get the answer . please help me to solve this.

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Synthesizability rules are ultimately up to the HLS synthesis vendor, and they are definitely different between vendors. The synthesizable subset standard is simply a guideline of commonly agreed upon constructs that either clearly able to be synthesized (e.g. sc_signal) or not (e.g. new and delete). Every synthesis tool will have some variance. Please refer to your sythesis vendor's reference manual to learn their rules. If that fails, contact their support.

Simulation does not guarantee synthesizability.

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 I have referred (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug902-vivado-high-level-synthesis.pdf ) the design guide page no:379 and it says that it can be synthesized... 

Is there any other tool like vivado hls to synthesize my code?   or  is there any documents to know things more about the usage guides for sc_fifo  to make it synthesizable?

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