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Everything posted by Dinesh

  1. I have referred (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug902-vivado-high-level-synthesis.pdf ) the design guide page no:379 and it says that it can be synthesized... Is there any other tool like vivado hls to synthesize my code? or is there any documents to know things more about the usage guides for sc_fifo to make it synthesizable?
  2. Hello, I am trying to connect a custom fifo between 2 modules, that works fine in simulation and verification in my linux and also vivado hls but when i try to synthesize it using vivado hls , it give an error as, ERROR: [SYNCHK 200-91] Port 'imp.cons.in.m_if.Val.data' (../final/p.h:200) of function 'center_detector' cannot be set to a FIFO ERROR: [SYNCHK 200-91] as it has both write (../final/x.h:19:17) and read (../final/y.cpp:9:4) operations. Is that synthesizable or not ? sc_port<sc_fifo_out_if<line> >out; // producer module port sc_port<sc_fifo_in_if<line> > in; // consumer module port my read and write operations as out->write(f); in->read(f); I saw this similar topic in https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/SystemC-sc-fifo-and-hierarchy/td-p/741511 , but i couldn't get the answer . please help me to solve this.
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