I am trying to connect a custom fifo between 2 modules, that works fine in simulation and verification in my linux and also vivado hls but when i try to synthesize it using vivado hls , it give an error as,
ERROR: [SYNCHK 200-91] Port 'imp.cons.in.m_if.Val.data' (../final/p.h:200) of function 'center_detector' cannot be set to a FIFO
ERROR: [SYNCHK 200-91] as it has both write (../final/x.h:19:17) and read (../final/y.cpp:9:4) operations.
Is that synthesizable or not ?
sc_port<sc_fifo_out_if<line> >out; // producer module port
sc_port<sc_fifo_in_if<line> > in; // consumer module port
my read and write operations as
I saw this similar topic in https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/SystemC-sc-fifo-and-hierarchy/td-p/741511 , but i couldn't get the answer . please help me to solve this.