nosnhojn Posted February 2, 2012 Report Share Posted February 2, 2012 This seems like it should be a simple question... I have a testbench that includes uvm components A and B. With both instantiated, I'd like to be able to control whether or not either/both are actually used in a given test. What would I have to do to have either of those components ignored during at least the runtime phases? -neil Quote Link to comment Share on other sites More sharing options...
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