nosnhojn Posted February 2, 2012 Report Share Posted February 2, 2012 This seems like it should be a simple question... I have a testbench that includes uvm components A and B. With both instantiated, I'd like to be able to control whether or not either/both are actually used in a given test. What would I have to do to have either of those components ignored during at least the runtime phases? -neil Quote Link to comment Share on other sites More sharing options...
dave_59 Posted February 2, 2012 Report Share Posted February 2, 2012 It depends what you mean by "actually used". More specifically, what it means to ignore them, assuming there are already there. Do you simply mean you don't what their run phases to execute? what about the other phases? At what point do you know that you want to ignore them? If the top-level test knows at the build_phase that they are to be ignored, why build them? You can use the factory to override the component with another whose run_phase it an empty stub. Quote Link to comment Share on other sites More sharing options...
nosnhojn Posted February 2, 2012 Author Report Share Posted February 2, 2012 dave, the scenario is a test that goes through a number of restarts. I'm setup to jump back from shut down to reset which is working well. Next is that for a given cycle through the run phases, I'd like to selectively turn off a component. Boiled down, I'd like to go through the common phases for all the components in the testbench, then select which components go through the run phases. The components that are idle don't have their run phase methods invoked. That enough info? thanks -neil Quote Link to comment Share on other sites More sharing options...
nosnhojn Posted February 2, 2012 Author Report Share Posted February 2, 2012 You can use the factory to override the component with another whose run_phase it an empty stub Is this something I can do at the beginning of each iteration through the run phases? overriding a component with another that has an empty run phase would be just as good as the original sitting idle. Quote Link to comment Share on other sites More sharing options...
nosnhojn Posted February 2, 2012 Author Report Share Posted February 2, 2012 Is this something I can do at the beginning of each iteration through the run phases? Pretty sure that was a stupid question... can't override components after the build. Quote Link to comment Share on other sites More sharing options...
uwes Posted February 3, 2012 Report Share Posted February 3, 2012 hi, you cannot change the static topology (=creating any components) once you pass start_of_simulation BUT what you can do is to build all components and then dynamically switch them active or passive.you can silence the sequencers/drivers/... /uwe Quote Link to comment Share on other sites More sharing options...
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