Behavioral XOR Gate with Delay

[re1418ma]

hi Is it possible to write behavioral xor gate just like AND gate in systemc?

and how i should add certain amount of delay?

[AmeyaVS]

Hello @re1418ma,

This has been already discussed before here:

http://forums.accellera.org/topic/5715-delaying-simulated-execution/

Hope it helps and if you have further questions please feel to ask.

Regards,

Ameya Vikram Singh

[re1418ma]

#include "systemc.h"
SC_MODULE(and2)
{
sc_in<bool> A, B;
sc_out<bool> F;
void do_and2()
{
F.write( A.read() && B.read() );
}
SC_CTOR(and2)
{
SC_METHOD(do_and2);
sensitive << A << B;
}
};

Thanks for reply

i use this code for AND Gate What changes should be made؟

[AmeyaVS]

Hello @re1418ma,

You can look at this example:

http://forums.accellera.org/topic/5678-clock-to-q-propagation-delay/?do=findComment&comment=13657

Or this one which shows how to add delay in full adder:

http://forums.accellera.org/topic/5715-delaying-simulated-execution/?do=findComment&comment=13844

Hope it helps.

Regards,

Ameya Vikram Singh