re1418ma

hi i'm trying

hi to all I'm writing code for DDT and I've been severely torn in terms of time Has anyone implemented this issue before so i can use it?

#include "systemc.h" #include "systemc-ams.h" SC_MODULE (lpf) { sca_eln::sca_terminal a; sca_eln::sca_terminal b; sca_eln::sca_r r1; sca_eln::sca_c c1; SC_CTOR(lpf) :a("a"),b("b"),r1("r1",10e3),c1("c1",100e-6),gnd("gnd") { r1.p(a); r1.n(b); c1.p(b); c1.n(gnd); } private: sca_eln::sca_node_ref gnd; }; hi to all i wrote this code for eln low pass filter how should i test it?

you helped a lot sir and for final question i read the post about delay and make some changes #include "systemc.h" SC_MODULE(and_gate){ sc_in<bool> a, b; sc_out<bool> c; void and_gate_p(){ while(true){ wait(5,SC_NS); c.write(a.read() & b.read()); } } SC_CTOR(and_gate){ SC_THREAD(and_gate_p); sensitive << a << b; } }; int sc_main(int argc, char* argv[]){ sc_signal<bool> a, b, c; and_gate and1("and_gate_and1"); and1.a(a); and1.b(b); and1.c(c); sc_trace_fi

i've searched whole my computer and only found object and source code

thanks for reply i removed next_trigger and code build succeeded this seems stupid question where vcd trace file located?

the gate must have delay of 5ns removing that statement and still getting error

thanks for the reply i wrote this code #include "systemc.h" SC_MODULE(and_gate){ sc_in<bool> a, b; sc_out<bool> c; void and_gate_p(){ next_trigger(5, SC_NS); c.write(a.read() & b.read()); } SC_CTOR(and_gate){ SC_METHOD(and_gate_p); sensitive << a << b; } }; int sc_main(int argc, char* argv[]){ sc_signal<bool> a, b, c; and_gate and1("and_gate_and1"); and1.a(a); and1.b(b); and1.c(c); sc_trace_file *tf = sc_create_vcd_trace_file("and_gate"); tf->set_time_unit(1, SC_NS

hi i installed systemc in microsoft visual studio and i wrote some code now i want to see output wave in gtkwave how should i export my code to see waves in gtkwave?

#include "systemc.h" SC_MODULE(and2) { sc_in<bool> A, B; sc_out<bool> F; void do_and2() { F.write( A.read() && B.read() ); } SC_CTOR(and2) { SC_METHOD(do_and2); sensitive << A << B; } }; Thanks for reply i use this code for AND Gate What changes should be made؟

hi Is it possible to write behavioral xor gate just like AND gate in systemc? and how i should add certain amount of delay?