Delaying simulated execution

[katang]

Is there a facility for simulation to delay execution? (something like #time in Verilog). Something like sc_sleep(time). (see http://stackoverflow.com/questions/26125756/systemc-module-not-working-with-sc-thread)

I understand it would not result in a timed simulation, but would be good for educational purposes.

[AmeyaVS]

Hello Katang,

This has been already discussed previously.

Take a look here:

Quote

 

-Ameya Vikram Singh

[katang]

Thanks for the hint. How delay_transport should be used? My attempt is below. It compiles and runs, but has no effect on the simulated time.

 

     SC_MODULE (BIT_ADDER)
      {
        sc_in<sc_logic> a,b,cin;
        sc_out<sc_logic> sum,cout;

        SC_CTOR (BIT_ADDER)
        {
             SC_METHOD (process);
             sensitive << a << b << cin;
        }

        void process()
        {
              //Declare variables of type "logic" to be used in calculations
             sc_logic aANDb,aXORb,cinANDaXORb;
             sc_time tdelay( 2, SC_NS);
             delay_transport<sc_time>  DT(BIT_ADDER, sc_time tdelay);

             aANDb = a.read() & b.read();
             aXORb = a.read() ^ b.read();
             DT;
             cinANDaXORb = cin.read() & aXORb;

             //Calculate sum and carry out of the 1-BIT adder
             sum = aXORb ^ cin.read();
             cout = aANDb | cinANDaXORb;
         }

       }; 

 

[AmeyaVS]

Hello @katang,

It would be better that you start here from this tutorial:

https://www.doulos.com/knowhow/systemc/tutorial/modules_and_processes/

Then refer the earlier post for delay simulation:

Quote

 

Checkout my reply to the post which references this:

http://workspace.accellera.org/Discussion_Forums/helpforum/archive/msg/msg?list_name=help_forum&monthdir=200803&msg=msg00061.html

Finally check my comment on how to do away with the SC_THREAD to improve performance of the simulation:

Quote

 

in-case you have more questions or need more elaboration on the answer let me know.

Regards,

Ameya Vikram Singh

[katang]

Hi,

What is wrong with my implementation? I receive the error message

Quote

Error: (E112) get interface failed: port is not bound: port 'BitAdder1.BIT_ADDER_DELAY2.in' (sc_in)

I guess I am making the instance at the wrong place/time. What is the expected way of utilization?

SC_MODULE (BIT_ADDER)
{
  sc_in<sc_logic> a,b,cin;
  sc_out<sc_logic> sum,cout;
  sc_signal<sc_logic>  X,Y;
  delay_inertial<sc_logic> DTT{"BIT_ADDER_DELAY2", sc_time(2, SC_NS)};
  SC_CTOR (BIT_ADDER)
  {
       SC_METHOD (process);
       sensitive << a << b << cin;
  }

  void process()
  {
         sc_logic aANDb,aXORb,cinANDaXORb;
       sc_signal<sc_logic>  X,Y;
       DTT.in (Y) ; DTT.out (Y) ;

        aANDb = a.read() & b.read();
       aXORb = a.read() ^ b.read();
       cinANDaXORb = cin.read() & aXORb;
       Y.write(aANDb); X.write(aXORb);

       cout = Y.read() | cinANDaXORb;
       sum = X.read() ^ cin.read();
   }
 }; 

 

[AmeyaVS]

Hello @katang,

Here is a modified source for Bit_Adder.h which emulates the delay between component/modules:

#ifndef BIT_ADDER_H_
#define BIT_ADDER_H_

#include <systemc>
#include <queue>

template<typename T = bool>
SC_MODULE(BIT_ADDER)
{
  public:
    sc_core::sc_in<T> a, b, cin;
    sc_core::sc_out<T> sum, cout;

    SC_CTOR(BIT_ADDER):
      a("a")
      , b("b")
      , ci("cin")
      , sum("sum")
      , cout("cout")
      , delay(sc_core::sc_time(2, sc_core::SC_NS))
      , eqSum("eqSum")
      , eqCarry("eqCarry")
    {
      SC_METHOD(do_add);
      sensitive << a << b << cin;
      dont_initialize();

      SC_METHOD(drive_sum);
      sensitive << eqSum;
      dont_initialize();

      SC_METHOD(drive_carry);
      sensitive << eqCarry;
      dont_initialize();
    }

    void do_add(void)
    {
      T valA = a.read();
      T valB = b.read();
      T valCi = cin.read();

      T tmpCo = (valA & valB) | (valB & valCi) | (valA & valCi);
      T tmpSum = valA ^ valB ^ valCi;

      coq.push(tmpCo);
      sumq.push(tmpSum);

      eqSum.notify(delay);
      eqCarry.notify(delay);
    }

    void drive_sum(void)
    {
      T valSum = sumq.front();
      sum.write(valSum);
      sumq.pop();
    }

    void drive_carry(void)
    {
      T valCarry = coq.front();
      cout.write(valCarry);
      coq.pop();
    }

  private:
    sc_core::sc_time delay;
    sc_core::sc_event_queue eqSum;
    sc_core::sc_event_queue eqCarry;
    std::queue<T> sumq;
    std::queue<T> coq;

}; // BIT_ADDER

#endif // BIT_ADDER_H_

This should be drop-in replacement for your module.

One thing you will have to change is the declaration where it would change something from:

BIT_ADDER bitAdder

to:

BIT_ADDER<sc_logic> bitAdder

Let us know if you need further clarification on how the module behavior is modeled.

Regards,

Ameya Vikram Singh

[katang]

Hello @AmeyaVS,

thanks for providing this solution. It helped more than reading a chapter in a book about SystemC. Could you please add one explanation?

You provided a hint to a delay unit previously, which you did not use here. Did you so because of performance of didactic reasons?