enchanter Posted November 13, 2017 Report Share Posted November 13, 2017 I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals. I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it looks the simulation will never finish. So would someone let me know what's the right way to handle the clock and reset signals? Quote Link to comment Share on other sites More sharing options...
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