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  1. Hi, I addressed this by creating a sc_module to generate clock and reset. Clock is a sc_clock signal and the module had a sc_thread for reset generation. This module was instantiated in sc_main and the clock was connected to the DUT using an sc_signal. You ca give this a try. Thanks Akhila
  2. Anyone who knows the current status of coverage support in UVM SC?
  3. Does UVM_SC has support for coverage bin and coverpoints? Want to know if user can add functional coverage classes. Thanks Akhila
  4. Hi All, I integrated SCV library in my environment and I am able to randomize my sequence item using SCV_EXTENSIONS and scv_smart_ptr. I still couldn't figure out the issue with UVM_DO* macros. But have found a way to randomize the transactions. Thanks Akhila
  5. Hi All, Just wanted to check if the UVM sequence macros (UVM_DO_ON_WITH and UVM_DO_WITH) which support randomizing the sequence object are yet supported by UVM-SC or not? If not, what is the best way to add some randomization in the framework? I saw a post where there are some snippets (link given below) using scvx_rand_object class but I am not sure where to find this(didn't find it in latest SCV and UVM-SC libraries). http://nascug.org/events/20th/1-NASCUG20-UVMforSystemC-Karsten.pdf Also, I get errors while using plain UVM_DO_ON macros. Is it expected? The same works fine wi
  6. Hi Martin, I tried adding callback dropped to my top level test. I can that objection->get_objection_total(this) is returning 0 whereas objection->get_objection_total(uvm_root::get()) is returning 1. So this tells that there is some objection pending. Now when I added all_dropped callback to the test, its also executing. This implies that there is no pending objection for this class and its children correct? And the pending one is from uvm_top as shown by display_objections() method(pasted the output below). Any idea from where is this getting generated? 0 s: UVM te
  7. Thanks Martin. I looked at the example you mentioned. I will add call to get_objection() in my test's run_phase and check. But if i call display_objections() in final_phase and find the count to be 0, wouldn't this imply there are no pending objections? Also, will the simulation enter into subsequent phases (viz. final, report), if there is a pending objection in previous phase( viz. run_phase) ? Thanks Akhila
  8. Hello All, Another update from my side here: I could query the objections in final_phase of my test and saw that there were no pending ones. I had to explicitly call sc_stop() and only then end_of_simulation method was called by the simulator. is it the expected behavior? Pasted the updated methods in my test: virtual void final_phase(uvm::uvm_phase& phase) { std::cout << sc_core::sc_time_stamp() << ": Final phase of test entered " << name() << std::endl; uvm_objection* uvm_obj; uvm_obj = new uvm_obje
  9. Hi All, I found one basic issue with the run phase method in driver. There was a typo. I used run_phase(uvm_phase phase), instead of run_phase(uvm_phase& phase). So the phase was not passed by reference, hence I think the phases in driver class were not in sync with other classes. Sorry about that, i too spent a lot of time in figuring this out :(. Now I can see that the simulation enters all run_phases (i.e. of test and driver) and exits after the sequence is over. But even though all phases are exited, the simulation is getting stuck. I believe in UVM-SC also w
  10. Hi Guys, Not sure if someone else has faced similar issue. After little more debug the issue seems to be with the simulator not entering into driver's run_phase at all. Ideally all run phases should be executed in parallel. Currently it gets stuck after the sequence raises objection and times out. Please let me know if I can try some alternatives. Thanks Akhila
  11. Hi Guys, I have a simple framework for an IP level testbench, written using UVM-SC libraries. The intent is to be able to pump basic AHB write/read request to the DUT(in System C) using this BFM. I have created all basic components, snippet for which are pasted below. I have an ahb_sequencer, which is just an extension oh uvm_sequencer with specific ahb_transaction type. In ahb_driver run_phase is as under: void run_phase(uvm::uvm_phase phase) { REQ req, rsp; for(;;) { UVM_INFO(this->get_name(), "
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