Jump to content

UVM Override V/s Simulator Compile/Elab

Recommended Posts

Hi Folks, 

Interestingly today making some tweaks I faced a scenario with overrides.

Suppose I add some variables in the extended class which are not present in the base class.

Then I called the uvm_set_type_override from my top test.

Interestingly I wanted to access those newly added variables in final_phase of some component , but during the simulator compile/elaboration phase it fails since the overrides are active during Simulation run-UVM_BUILD_PHASE.

So my question is , if someone using some legacy code and wanted to update the stuff without re-writing again/or major changes , extended from base, then only overrides possible are those that will be active during simulation run , for an example , setting default sequence to driver with override.

So there is no way we could leverage it.

I am wandering , if TLM-GP extensions implementation may provide my some idea to do this.

Any suggestions ???

If needed a code to see  I saved the stuff http://www.edaplayground.com/x/2Ltr

Line 156 is point of interest




Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...