Adam Sherilog Posted December 6, 2011 Report Share Posted December 6, 2011 Wednesday December 7 at 11a ET, Cadence will explain UVM phasing in the cleverly titled "Set Your UVM Runtime Phases to Maximum Power" webinar. The seminar will be delivered by the legendary Uwe Simm whom you all know as a prolific contributor to the UVM technical forums. he Accellera Universal Verification Methodology (UVM), like the Open Verification Methodology (OVM) and the e Reuse Methodology (eRM) before it, divides the overall verification effort into multiple phases. Most of these do not consume simulation time but rather manage the construction and completion of the verification test. The run phase is the one in which time proceeds, tests inject stimulus, and monitors/scoreboards measure the responses. While some UVM verification components (UVCs) are simple enough to view this phase as atomic, others need to finely manage steps such as configuration, reset, and post-run clean-up. The UVM subdivides run and allow you to control testbench activity in each sub-phase. That may seem simple enough, but if your UVC does need these sub-phases, then you need to now manage its integration with UVCs that may or may not use sub-phases. Each UVC may need to jump forward or back through the sub-phases, and that coordination will need to be managed as well. Our verification expert Uwe Simm is the leading contributor to the bugs fixed in UVM and to the questions asked in these forums and will present the following topics: Identifying when UVM runtime phases are really required Basics of the UVM runtime phases â€“ what the UVM BCL provides Applying the runtime phases using the UVM Reference Flow Common problems and solutions when applying runtime phases The webinar will share the steps you need to determine if your UVC really needs runtime phases. If it does, the component is simpler to build and maintain. Assuming you are attending because you do need to apply them, the webinar will provide critical methodology guidelines to maximize the verification power you will derive from runtime phases and help you to avoid common pitfalls as you integrate your UVC into larger system verification environments. Quote Link to comment Share on other sites More sharing options...
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