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Adam Sherilog

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About Adam Sherilog

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  1. Aliu - we don't have HTML yet. Its is something we are considering but we don't have a plan yet. However, that is very good input! Leo - we are trying to update the user guide. We should have more information on what can be done after the next UVM working group meeting in early July. =Adam
  2. On behalf of the UVM Working Group (UVMWG), welcome to the public review forum for UVM 1.2. It includes enhanced messaging, improvements to the register layer and other features. As you use it we encourage you to post comments and suggestions to this forum. We've staffed the forum with some of the UVMWG experts to answer your questions and bring your suggestions into the committee. We will be analyzing them as part of an effort to take UVM 1.2 to the IEEE by October 1, 2014. You can find a direct Class Reference link here: http://www.accellera.org/downloads/standards/uvm/UVM_Class_Refer
  3. And just when you thought all of the above goodness was too good to be true, we have even more! UVM has been growing by leaps and bounds in China so we translated the video shorts into Chinese! Do to some restrictions in China, we have made the videos available on two sites: Link to YouTube Playlist (Chinese) Link to YouKu Playlist (Chinese) Link to YouTube Playlist (English) Link to YouKu Playlist (English) We would also like to introduce our third twin :-), Yi-Shiun Lin who did the work to translate these videos. Thank you! =Adam Sherilog on behalf of both of his twins Axel an
  4. Just when you thought 24 videos about UVM were enough, we added more! This video walks you through the UVM Class Library pointing out key aspects that are important to all UVM developers. It's your coffee break, so grab a fresh cup and enjoy! http://www.cadence.com/Community/blogs/fv/archive/2012/07/16/uvm-systemverilog-class-library-overview-video-inspired-by-1600-cowbells-in-action.aspx =Adam Sherilog on behalf of Cadence's prolific video presence, and my twin brother, Axel Scherer
  5. All, Axel Scherer manages a team of UVM experts and has recorded their collected experience in a series of 24 UVM SystemVerilog basics videos. Each video is between 2 and 5 minutes making them easy to view when you have some free time, and easy to review when you're looking for a refresher. The videos are open to all viewers with no registration required. Just a little Cadence EDA360 to help the UVM community. http://www.youtube.com/playlist?list=PL7FE0CE1170C06FDE The initial set of topics include the following and we expect to do more in the future: Introducing UVM Example DUT
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