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Adam Sherilog

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Everything posted by Adam Sherilog

  1. You have a need for speed. Everyone does. But not a small need. You have a big need. Not a 2X need. A much bigger need. The kind of need that can only be satisfied with Palladium, the best hardware accelerator available. Axel Scherer, my Cadence brother, recorded this video to show how you can run your UVM environment in simulation and acceleration. Spend 5 min to learn how you can quench your need for speed. http://youtu.be/2S4NIrOT9XE?list=PLYdInKVfi0KZqWOWeDTa58tuBD-5S7HQC Fast simulation. Fast acceleration. Fast post. Enjoy. =Adam Sherer, Cadence
  2. Hello Everyone, Cadence recently released an update to its UVM multi-language (ML) open architecture library. This version 1.4 is available in the Accellera Upload area at: http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/ For more information, you can see this blog posted at Cadence.com: http://www.cadence.com/Community/blogs/fv/archive/2014/06/03/updates-from-the-uvm-multi-language-ml-front.aspx?postID=1334799 =Adam "ML" Sherilog
  3. Hi, I think this question, especially for a particular set of product licenses, is best answered by Cadence support. But the IES vs IUS I can answer here. IES, the Incisive Enterprise Simulator, has two product configurations L and XL. The IES-XL is the one you should use if you previously purchased IUS (Incisive Unified Simulator). IES-XL is a whole superset of IUS and can run any scripts created using IUS. =Adam Sherer, Incisive Simulation Product Manager
  4. Folks, We had some complaints about this thread. If there is truly a tools-related issue, that should be directed to the vendor's support team. We shouldn't use these forums to suggest that users of vendor X would be better off with vendor Y. If a vendor has something to promote, that should be handled in the "Simulator Specific" or "Commercial" forums. =Adam Sherer Accellera Promotions Committee Vice-Chair
  5. The DVClub meeting September 9 is 100% dedicated to you all reading this forum -- UVM and SystemVerilog. We'll have four topics in this fast-moving event: Update from the Accellera UVM Working Group UVM Register Modelling: Advanced Topics SystemVerilog Scheduling Semantics Advanced Scoreboarding Techniques Using UVM You can register for the event here: http://dvclubsept2013.eventbrite.com/#! On behalf of the other presenters, we are looking forward to seeing or hearing you there! =Adam Sherer, UVM WG Secretary
  6. One aspect that was not covered in the UVM Basics series posted by Cadence in May 2012 was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer. The new video series is broken up into twelve clips: Introduction Testbench Integration Adapter Predictor & Auto Predict Register Model & Generation IP-XACT Register Model Classes Register API & Sequences Access Policies Frontdoor & Backdoor Predefined Sequences Demonstration You are now registered for success! (sorry, bad pun
  7. You can also find the release notes on the accellera.org site. The 1.1c notes show the delta from 1.1b. By Accellera rules, the [abc*] releases do not change the standard. =Adam
  8. Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple language in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Cadence saw this need in the years leading to the UVM and was the first to contribute a multi-language solution. This solution was updated several times during the past four years to remain synchronized with UVM and add new functionality. On Thursday October 25 at 9a PDT we'll review the solution and discuss new features.
  9. It's here! The UVM 1.1c release is now available for immediate download on the Accellera Website at http://www.accellera.org/downloads/standards/uvm. Enjoy! =Adam Sherer, Accellera VIPTSC Secretary
  10. And just when you thought all of the above goodness was too good to be true, we have even more! UVM has been growing by leaps and bounds in China so we translated the video shorts into Chinese! Do to some restrictions in China, we have made the videos available on two sites: Link to YouTube Playlist (Chinese) Link to YouKu Playlist (Chinese) Link to YouTube Playlist (English) Link to YouKu Playlist (English) We would also like to introduce our third twin :-), Yi-Shiun Lin who did the work to translate these videos. Thank you! =Adam Sherilog on behalf of both of his twins Axel an
  11. Just when you thought 24 videos about UVM were enough, we added more! This video walks you through the UVM Class Library pointing out key aspects that are important to all UVM developers. It's your coffee break, so grab a fresh cup and enjoy! http://www.cadence.com/Community/blogs/fv/archive/2012/07/16/uvm-systemverilog-class-library-overview-video-inspired-by-1600-cowbells-in-action.aspx =Adam Sherilog on behalf of Cadence's prolific video presence, and my twin brother, Axel Scherer
  12. The Accellera Systems Initiative Verification IP Technical Subcommittee (aka UVM) has approved the UVM 1.1b for immediate release. You can download it now at http://www.accellera.org/downloads/standards/uvm and the links from UVMWorld are being updated to point to it. We have also had numerous requests to make the release notes and user guide available both inside and outside of the tarball. You can find direct links to both documents on the downloads page and here: UVM 1.1b tarball UVM 1.1b release notes UVM 1.1 user guide UVM 1.1b closes more than 40 Mantis items and represents the c
  13. All, Axel Scherer manages a team of UVM experts and has recorded their collected experience in a series of 24 UVM SystemVerilog basics videos. Each video is between 2 and 5 minutes making them easy to view when you have some free time, and easy to review when you're looking for a refresher. The videos are open to all viewers with no registration required. Just a little Cadence EDA360 to help the UVM community. http://www.youtube.com/playlist?list=PL7FE0CE1170C06FDE The initial set of topics include the following and we expect to do more in the future: Introducing UVM Example DUT
  14. The Accellera Systems Initiative Verification IP Technical Subcommittee (we have ENORMOUS business cards ) has approved the UVM 1.1a for immediate release. You can download it now at http://www.accellera.org/downloads/standards/uvm and the links from UVMWorld are being updated to point to it. UVM 1.1a closes more than 60 Mantis items and represents the combined contributions from multiple committee members. Once again, the team working on UVM proves that industry-wide collaboration not only works but can produce something can makes us all proud. =Adam Sherer, VIPTSC (UVM) Secretary
  15. Wednesday December 7 at 11a ET, Cadence will explain UVM phasing in the cleverly titled "Set Your UVM Runtime Phases to Maximum Power" webinar. The seminar will be delivered by the legendary Uwe Simm whom you all know as a prolific contributor to the UVM technical forums. he Accellera Universal Verification Methodology (UVM), like the Open Verification Methodology (OVM) and the e Reuse Methodology (eRM) before it, divides the overall verification effort into multiple phases. Most of these do not consume simulation time but rather manage the construction and completion of the verification te
  16. Just a quick reminder, Cadence will host a webinar today describing the integration of SystemC with UVM SystemVerilog. This is a technical webinar describing the requirements for such an integration and the solution available to meet many of those requirements. Phu Huynh will walk through the solution and an example as part of the webinar. http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=558 =Adam Sherer, Cadence
  17. On June 7, 2011 the Accellera Board approved the UVM 1.1 update and release. The updated BCL and user guide are available for immediate download from the only official source http://www.accellera.org/activities/vip. While this is primarily a bug-fix release, we do recommend that you review the release notes in the tar file to understand the changes from 1.0 to 1.1. =Brought to you by the 325 members of the Accellera VIP TSC
  18. Talk about stability -- OVM 2.1.1 has had 18 months as the core of Accellera's UVM and accumulated only 13 bugs. Not too shabby! With the OVM community preparing to migrate, Cadence and Mentor have posted a bug-fix update -- OVM 2.1.2 -- to OVMWorld to help you get ready to move to the UVM. As you may have seen in my twitter feed, I've been out talking to customers a lot lately. Both OVM and VMM users have been telling me they are really happy that UVM is here and are preparing to migrate. On the OVM side, we've heard consistently "we are preparing to migrate at the end of this project, b
  19. The UVM Reference Flow version 1.02 has been updated to align with the Accellera uvm-1.0 release (uvm-1.0p1). It applies the Universal Verification Methodology (UVM) to a block and cluster verification in a SoC design. The UVM Reference Flow was developed by Cadence to show the best practices for applying UVM to the verification of a block; a Universal Asynchronous Receiver Transmitter (UART). It then shows how to reuse the block level verification environment when verifying a cluster design (an APB subsystem) into which the UART is integrated along with other design components (viz. SPI, GPIO
  20. Why? Because everyone is doing it! Kidding aside, Jadec captured some solid points. Here are a few more. OVM users * Backward compatibility maintained in UVM 1.0. As more technology is added beyond 1.0, that compatibility may be harder to maintain if it is inappropriate for technical reasons. * Universal register package. OVM users had two packages available while UVM has one. * New phasing, configuration, command line, and TLM2 features. Without diving into each one here, there are several new features available to improve your verification VMM users * Demonstrated multi-
  21. Thanks for pinging this thread because I get that question a lot. The TSC is working hard to get the UVM 1.0 released this year. We do have a target of December 22 for a final completion, but we tend to like to release on a Monday so the library may well appear on the Accellera site on December 27. We also now have a program manager assigned to help the whole team work toward that deadline. Both Cadence and Mentor have been blogging on UVM 1.0 and each have some interesting information about the technical content. Since that work is still in-flight, I won't comment further but suggest you
  22. Hi All, As several have mentioned in this thread, the Accellera committee is currently working on a register package solution. There are a few packages converted to run with the UVM, including the Cadence package posed in the UVM contributions area http://www.uvmworld.org/contributions-details.php?id=83&keywords=Cadence_UVM_RGM2.2_Release. The Cadence package was converted from an OVM version so it has a heritage of compatibility with the BCL. Please keep in mind that NONE of the UVM register packages are official at this time. Here at DAC the chairs stated that the VIP TSC is worki
  23. Hello SeanChou, Any official roadmaps would be announced by the Accellera VIP TSC chairs Tom Alsop and Hillel Miller (I'm the secretary), but let me see if I can help with your questions based on the public discussions so far. 1. The TSC has not set a firm date yet as we are trying to finalize the content. For sure, a register package and a subset of OSCI-TLM2 are very high on the list. There are several other features on that list as well. I would expect that we will have a more solid release date after the TSC meets face to face later this summer. i will encourage Tom and Hillel to com
  24. Hi Veeramuthu, All three of the simulation vendors you mentioned support UVM today. Rather than speak for them all, I'll just put links for their statements. Synopsys: http://www.vmmcentral.org/vmartialarts/?p=1395 Mentor: http://blogs.mentor.com/verificationhorizons/blog/2010/05/17/accellera-omnimodus-verification-methodology/ Cadence: http://www.cadence.com/Community/blogs/ii/archive/2010/05/17/uvm-1-0-ea-is-available-what-this-means-to-you.aspx?postID=62148 =Adam Sherilog, Cadence
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