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Adam Sherilog

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Everything posted by Adam Sherilog

  1. You have a need for speed. Everyone does. But not a small need. You have a big need. Not a 2X need. A much bigger need. The kind of need that can only be satisfied with Palladium, the best hardware accelerator available. Axel Scherer, my Cadence brother, recorded this video to show how you can run your UVM environment in simulation and acceleration. Spend 5 min to learn how you can quench your need for speed. http://youtu.be/2S4NIrOT9XE?list=PLYdInKVfi0KZqWOWeDTa58tuBD-5S7HQC Fast simulation. Fast acceleration. Fast post. Enjoy. =Adam Sherer, Cadence
  2. Aliu - we don't have HTML yet. Its is something we are considering but we don't have a plan yet. However, that is very good input! Leo - we are trying to update the user guide. We should have more information on what can be done after the next UVM working group meeting in early July. =Adam
  3. On behalf of the UVM Working Group (UVMWG), welcome to the public review forum for UVM 1.2. It includes enhanced messaging, improvements to the register layer and other features. As you use it we encourage you to post comments and suggestions to this forum. We've staffed the forum with some of the UVMWG experts to answer your questions and bring your suggestions into the committee. We will be analyzing them as part of an effort to take UVM 1.2 to the IEEE by October 1, 2014. You can find a direct Class Reference link here: http://www.accellera.org/downloads/standards/uvm/UVM_Class_Reference_Manual_1.2.pdf You can find a direct tarball link here: http://www.accellera.org/downloads/standards/uvm/uvm-1.2.tar.gz Thank you for your help and we look forward to some interesting technical discussions. Regards, Adam Sherer, UVMWG Secretary
  4. Hello Everyone, Cadence recently released an update to its UVM multi-language (ML) open architecture library. This version 1.4 is available in the Accellera Upload area at: http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/ For more information, you can see this blog posted at Cadence.com: http://www.cadence.com/Community/blogs/fv/archive/2014/06/03/updates-from-the-uvm-multi-language-ml-front.aspx?postID=1334799 =Adam "ML" Sherilog
  5. Hi, I think this question, especially for a particular set of product licenses, is best answered by Cadence support. But the IES vs IUS I can answer here. IES, the Incisive Enterprise Simulator, has two product configurations L and XL. The IES-XL is the one you should use if you previously purchased IUS (Incisive Unified Simulator). IES-XL is a whole superset of IUS and can run any scripts created using IUS. =Adam Sherer, Incisive Simulation Product Manager
  6. Folks, We had some complaints about this thread. If there is truly a tools-related issue, that should be directed to the vendor's support team. We shouldn't use these forums to suggest that users of vendor X would be better off with vendor Y. If a vendor has something to promote, that should be handled in the "Simulator Specific" or "Commercial" forums. =Adam Sherer Accellera Promotions Committee Vice-Chair
  7. The DVClub meeting September 9 is 100% dedicated to you all reading this forum -- UVM and SystemVerilog. We'll have four topics in this fast-moving event: Update from the Accellera UVM Working Group UVM Register Modelling: Advanced Topics SystemVerilog Scheduling Semantics Advanced Scoreboarding Techniques Using UVM You can register for the event here: http://dvclubsept2013.eventbrite.com/#! On behalf of the other presenters, we are looking forward to seeing or hearing you there! =Adam Sherer, UVM WG Secretary
  8. One aspect that was not covered in the UVM Basics series posted by Cadence in May 2012 was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer. The new video series is broken up into twelve clips: Introduction Testbench Integration Adapter Predictor & Auto Predict Register Model & Generation IP-XACT Register Model Classes Register API & Sequences Access Policies Frontdoor & Backdoor Predefined Sequences Demonstration You are now registered for success! (sorry, bad pun. ) =Adam Sherilog, Cadence
  9. You can also find the release notes on the accellera.org site. The 1.1c notes show the delta from 1.1b. By Accellera rules, the [abc*] releases do not change the standard. =Adam
  10. Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple language in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Cadence saw this need in the years leading to the UVM and was the first to contribute a multi-language solution. This solution was updated several times during the past four years to remain synchronized with UVM and add new functionality. On Thursday October 25 at 9a PDT we'll review the solution and discuss new features. Join us through this link: http://www.cadence.com/cadence/events/Pages/eventseries.aspx?series=Functional%20Verification%20Webinar%20Series%202012&CMP=Home =Adam Sherer, Cadence
  11. It's here! The UVM 1.1c release is now available for immediate download on the Accellera Website at http://www.accellera.org/downloads/standards/uvm. Enjoy! =Adam Sherer, Accellera VIPTSC Secretary
  12. And just when you thought all of the above goodness was too good to be true, we have even more! UVM has been growing by leaps and bounds in China so we translated the video shorts into Chinese! Do to some restrictions in China, we have made the videos available on two sites: Link to YouTube Playlist (Chinese) Link to YouKu Playlist (Chinese) Link to YouTube Playlist (English) Link to YouKu Playlist (English) We would also like to introduce our third twin :-), Yi-Shiun Lin who did the work to translate these videos. Thank you! =Adam Sherilog on behalf of both of his twins Axel and Yi-Shiun
  13. Just when you thought 24 videos about UVM were enough, we added more! This video walks you through the UVM Class Library pointing out key aspects that are important to all UVM developers. It's your coffee break, so grab a fresh cup and enjoy! http://www.cadence.com/Community/blogs/fv/archive/2012/07/16/uvm-systemverilog-class-library-overview-video-inspired-by-1600-cowbells-in-action.aspx =Adam Sherilog on behalf of Cadence's prolific video presence, and my twin brother, Axel Scherer
  14. The Accellera Systems Initiative Verification IP Technical Subcommittee (aka UVM) has approved the UVM 1.1b for immediate release. You can download it now at http://www.accellera.org/downloads/standards/uvm and the links from UVMWorld are being updated to point to it. We have also had numerous requests to make the release notes and user guide available both inside and outside of the tarball. You can find direct links to both documents on the downloads page and here: UVM 1.1b tarball UVM 1.1b release notes UVM 1.1 user guide UVM 1.1b closes more than 40 Mantis items and represents the combined contributions from multiple committee members. The Chairs would like to thank the worldwide community for their use of UVM and their timing reporting of bugs. =Adam Sherer, VIPTSC (UVM) Secretary
  15. All, Axel Scherer manages a team of UVM experts and has recorded their collected experience in a series of 24 UVM SystemVerilog basics videos. Each video is between 2 and 5 minutes making them easy to view when you have some free time, and easy to review when you're looking for a refresher. The videos are open to all viewers with no registration required. Just a little Cadence EDA360 to help the UVM community. http://www.youtube.com/playlist?list=PL7FE0CE1170C06FDE The initial set of topics include the following and we expect to do more in the future: Introducing UVM Example DUT UVM Environment Interface UVC Collector Monitor Sequence Item Sequence Driver Sequencer Agent Agent types Interface UVC environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases Objections Virtual Interface =Adam Sherilog Cadence Verification Product Director
  16. The Accellera Systems Initiative Verification IP Technical Subcommittee (we have ENORMOUS business cards ) has approved the UVM 1.1a for immediate release. You can download it now at http://www.accellera.org/downloads/standards/uvm and the links from UVMWorld are being updated to point to it. UVM 1.1a closes more than 60 Mantis items and represents the combined contributions from multiple committee members. Once again, the team working on UVM proves that industry-wide collaboration not only works but can produce something can makes us all proud. =Adam Sherer, VIPTSC (UVM) Secretary
  17. Wednesday December 7 at 11a ET, Cadence will explain UVM phasing in the cleverly titled "Set Your UVM Runtime Phases to Maximum Power" webinar. The seminar will be delivered by the legendary Uwe Simm whom you all know as a prolific contributor to the UVM technical forums. he Accellera Universal Verification Methodology (UVM), like the Open Verification Methodology (OVM) and the e Reuse Methodology (eRM) before it, divides the overall verification effort into multiple phases. Most of these do not consume simulation time but rather manage the construction and completion of the verification test. The run phase is the one in which time proceeds, tests inject stimulus, and monitors/scoreboards measure the responses. While some UVM verification components (UVCs) are simple enough to view this phase as atomic, others need to finely manage steps such as configuration, reset, and post-run clean-up. The UVM subdivides run and allow you to control testbench activity in each sub-phase. That may seem simple enough, but if your UVC does need these sub-phases, then you need to now manage its integration with UVCs that may or may not use sub-phases. Each UVC may need to jump forward or back through the sub-phases, and that coordination will need to be managed as well. Our verification expert Uwe Simm is the leading contributor to the bugs fixed in UVM and to the questions asked in these forums and will present the following topics: Identifying when UVM runtime phases are really required Basics of the UVM runtime phases – what the UVM BCL provides Applying the runtime phases using the UVM Reference Flow Common problems and solutions when applying runtime phases The webinar will share the steps you need to determine if your UVC really needs runtime phases. If it does, the component is simpler to build and maintain. Assuming you are attending because you do need to apply them, the webinar will provide critical methodology guidelines to maximize the verification power you will derive from runtime phases and help you to avoid common pitfalls as you integrate your UVC into larger system verification environments.
  18. Just a quick reminder, Cadence will host a webinar today describing the integration of SystemC with UVM SystemVerilog. This is a technical webinar describing the requirements for such an integration and the solution available to meet many of those requirements. Phu Huynh will walk through the solution and an example as part of the webinar. http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=558 =Adam Sherer, Cadence
  19. On June 7, 2011 the Accellera Board approved the UVM 1.1 update and release. The updated BCL and user guide are available for immediate download from the only official source http://www.accellera.org/activities/vip. While this is primarily a bug-fix release, we do recommend that you review the release notes in the tar file to understand the changes from 1.0 to 1.1. =Brought to you by the 325 members of the Accellera VIP TSC
  20. Talk about stability -- OVM 2.1.1 has had 18 months as the core of Accellera's UVM and accumulated only 13 bugs. Not too shabby! With the OVM community preparing to migrate, Cadence and Mentor have posted a bug-fix update -- OVM 2.1.2 -- to OVMWorld to help you get ready to move to the UVM. As you may have seen in my twitter feed, I've been out talking to customers a lot lately. Both OVM and VMM users have been telling me they are really happy that UVM is here and are preparing to migrate. On the OVM side, we've heard consistently "we are preparing to migrate at the end of this project, but it would be really good if the official OVM release could be updated one last time to support our legacy code." Mentor and Cadence have heard that and we provided that update as OVM 2.1.2. When you look at the release notes you'll see the 10 bugs that were fixed and the 3 small API changes. There are no new features in OVM -- all of our engineering work is focused on UVM. In fact, the changes to OVM are more or less back-ports from the work done on UVM. Bottom line -- think of this bug-fix release as the safety net that enables you to move to the UVM with confidence! Looking for another point of confidence? Come listen to Larry Ching of Boeing present his experiences migrating from OVM to UVM at the Accellera breakfast and again in the Cadence Theater at DAC on Tuesday June 7th. Adam Sherer
  21. The UVM Reference Flow version 1.02 has been updated to align with the Accellera uvm-1.0 release (uvm-1.0p1). It applies the Universal Verification Methodology (UVM) to a block and cluster verification in a SoC design. The UVM Reference Flow was developed by Cadence to show the best practices for applying UVM to the verification of a block; a Universal Asynchronous Receiver Transmitter (UART). It then shows how to reuse the block level verification environment when verifying a cluster design (an APB subsystem) into which the UART is integrated along with other design components (viz. SPI, GPIO, power controller, timers etc.). You can download this open source contribution here on UVMWorld.
  22. Why? Because everyone is doing it! Kidding aside, Jadec captured some solid points. Here are a few more. OVM users * Backward compatibility maintained in UVM 1.0. As more technology is added beyond 1.0, that compatibility may be harder to maintain if it is inappropriate for technical reasons. * Universal register package. OVM users had two packages available while UVM has one. * New phasing, configuration, command line, and TLM2 features. Without diving into each one here, there are several new features available to improve your verification VMM users * Demonstrated multi-vendor reuse. Among the release criteria for the UVM 1.0 reference library is that it runs on Cadence, Mentor, and Synopsys simulators and supports reuse among them. * New features. Depending upon the version of VMM that you are using, the features in UVM 1.0 may be new to you. * Larger ecosystem = more choice. As the industry moves to a single library and methodology, it the efficiency of training, VIP, services, tools, etc. companies will rise so you'll see a much bigger set of options to enhance your verification environment. =Adam Sherilog
  23. Thanks for pinging this thread because I get that question a lot. The TSC is working hard to get the UVM 1.0 released this year. We do have a target of December 22 for a final completion, but we tend to like to release on a Monday so the library may well appear on the Accellera site on December 27. We also now have a program manager assigned to help the whole team work toward that deadline. Both Cadence and Mentor have been blogging on UVM 1.0 and each have some interesting information about the technical content. Since that work is still in-flight, I won't comment further but suggest you keep checking back here on UVM World for further details. =Adam Sherer
  24. Hi All, As several have mentioned in this thread, the Accellera committee is currently working on a register package solution. There are a few packages converted to run with the UVM, including the Cadence package posed in the UVM contributions area http://www.uvmworld.org/contributions-details.php?id=83&keywords=Cadence_UVM_RGM2.2_Release. The Cadence package was converted from an OVM version so it has a heritage of compatibility with the BCL. Please keep in mind that NONE of the UVM register packages are official at this time. Here at DAC the chairs stated that the VIP TSC is working toward a goal of releasing UVM 1.0 with a register package and other features by the end of October. That release will be feature driven, so the data itself is tentative. Given that, you can move to the UVM today with confidence in the BCL, but understand that if you choose a register package it may change with the UVM 1.0 release. =Adam Sherer, Cadence Product Management and Accellera VIP TSC Secretary
  25. Hello SeanChou, Any official roadmaps would be announced by the Accellera VIP TSC chairs Tom Alsop and Hillel Miller (I'm the secretary), but let me see if I can help with your questions based on the public discussions so far. 1. The TSC has not set a firm date yet as we are trying to finalize the content. For sure, a register package and a subset of OSCI-TLM2 are very high on the list. There are several other features on that list as well. I would expect that we will have a more solid release date after the TSC meets face to face later this summer. i will encourage Tom and Hillel to comment here on UVM World when we have more firm information. 2. There is always the chance for improvement! :-) One great thing about this standards group is that the team believes in delivering the best, not the lowest common denominator. I believe that the TLM2 work will include some SystemC support as each member contributes their requirements. In fact, I will make sure that the TSC is aware of your request when we meet today. 3. This one, unfortunately, I can't predict because I am both a chair of the committee and a representative from Cadence. What I can say is something similar to my point in #2. The TSC has worked extremely well to honor the needs of the whole verification community without causing undo backward compatibility issues. JL Gray's survey showed multiple register packages in use so I believe the TSC will follow the same process that brought you UVM 1.0 EA: collect requirements, develop a specification, develop an implementation, validate, and deliver. While that might seem like it would lead to a long project, the level of experience among the users, service providers, and EDA companies in the TSC will surely Accellera-te :-) it. I hope that helps and I will encourage Tom and Hillel to respond as well. =Adam "Sherilog" Sherer
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