petermonsson Posted November 20, 2011 Report Share Posted November 20, 2011 Hi all, What is the preferred way of creating a [mytype]_sequencer. Using a typedef or extending uvm_sequencer? Best Regards Peter Quote Link to comment Share on other sites More sharing options...
bhunter1972 Posted November 21, 2011 Report Share Posted November 21, 2011 Extending. You'll eventually want more in there than the base class gives you. Quote Link to comment Share on other sites More sharing options...
petermonsson Posted November 21, 2011 Author Report Share Posted November 21, 2011 Are you sure? How often have you had to extend the uvm_sequencer? I can't imagine why I would want add anything to it. Best Regards Peter Quote Link to comment Share on other sites More sharing options...
Erling Posted November 21, 2011 Report Share Posted November 21, 2011 I subclass sequencers, but that is mainly because I add common functionality to all components, including sequencers. Subclassing may also be easier to understand for non-experts, since the typedef in SV does not work like typedef in C/C++. Also, I am not sure the fact that the uvm_sequencer does register with the factory is part of the standard (the ovm_sequencer does not register with the factory, if I remember correctly). Erling Quote Link to comment Share on other sites More sharing options...
uwes Posted November 21, 2011 Report Share Posted November 21, 2011 hi, you would use a derived class ("extending") if you intent to add functionality or additional members to this sequencer type. you can use a typedef to create a shorter name for the sequencer type. Quote Link to comment Share on other sites More sharing options...
petermonsson Posted November 21, 2011 Author Report Share Posted November 21, 2011 Hi all, Thank you all for your comments. It turns out that a typedef'ed mytype_sequencer works with mytype_sequencer::type_id::create("string", this); so that is not a problem. Best Regards Peter Quote Link to comment Share on other sites More sharing options...
bhunter1972 Posted November 21, 2011 Report Share Posted November 21, 2011 Are you sure? How often have you had to extend the uvm_sequencer? I can't imagine why I would want add anything to it. Best Regards Peter Your sequences are uvm_objects that have no relationship to the component hierarchy. But, they have back pointers (m_sequencer & p_sequencer) that can root them into the hierarchy. You could put a register file, or an analysis port, or a configuration class--or anything really--in your sequencer, and then through these pointers your sequences can interact with the rest of the environment. Quote Link to comment Share on other sites More sharing options...
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