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Subclassing vs. typedef uvm_sequencer

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I subclass sequencers, but that is mainly because I add common functionality to all components, including sequencers. Subclassing may also be easier to understand for non-experts, since the typedef in SV does not work like typedef in C/C++. Also, I am not sure the fact that the uvm_sequencer does register with the factory is part of the standard (the ovm_sequencer does not register with the factory, if I remember correctly).


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Are you sure? How often have you had to extend the uvm_sequencer? I can't imagine why I would want add anything to it.

Best Regards


Your sequences are uvm_objects that have no relationship to the component hierarchy. But, they have back pointers (m_sequencer & p_sequencer) that can root them into the hierarchy. You could put a register file, or an analysis port, or a configuration class--or anything really--in your sequencer, and then through these pointers your sequences can interact with the rest of the environment.

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