Class fields dependency

[icarus035]

Hi all. I have a question regarding definition of class members:

Is it possible to create a field in a class which existence will depend on the value of other field?

For example, something like:

typedef enum {RED, GREEN, BLUE} color_type;

class my_class;

color_type my_color;

// Only when my_color is RED, I want this class to have another field called my_data

if (my_color == RED) then (logic [7:0] my_data);

...

endclass: my_class

(sorry if any syntax errors)

I know this capability exists in e language (by using "when" construct) but I have not been able to find anything similar for SystemVerilog.

Thanks.

[krb]

No You cannot declare variables like this at run time.

NOTE: you cannot use logic to declare class members.

You could use `defines to declare variables at compile time

eg:

`define MY_COLOR_IS_RED 1
class my_class;
     color_type my_color;
     // Only when my_color is RED, I want this class to have another field called my_data
     `ifdef MY_COLOR_IS_RED
     rand bit [7:0] my_data;
     `endif
endclass

Not sure what your intentions are here, but this may be enough for you.

class my_class;
     color_type my_color;
     rand bit [7:0] my_data;
     constarint c_my_data_valid_only_when_color_red {
          ( (my_color != RED) -> (my_data == 0) );
     }
endclass

Edited November 1, 2011 by krb
make it clearer

[icarus035]

Thanks for this clarification, it is very useful to me.

By the way, why can't I use logic type inside the class? I think I used it many times but never got any compile or any other type of error because of this.

[aji.cvc]

E's when inheritance/AOP with determinant can be achieved using a "flat structure" in SV - i.e. declare all fields and guard them during pack/unpack/display etc.

It is not straight forward and requires some re-thinking especially if you are a die-hard Specman fan.

Regards

Ajeetha, CVC

www.cvcblr.com/blog

[jadec]

I don't think he was talking about the "logic" type. He meant that the structure of a class wasn't controllable via code (if, for). A more Verilog way to say it-- you can't use "generate" type structures in a class.

[krb]

I wasn't mentioning to the use of logic data type, but to logic in declaring class members.

I also changed your "logic [7:0] my_data" to bit type because the rand modifier only works on 2-state data types (bit).

You don't have to use the rand modifier, as I did in the example.

The constraint block will have no meaning without the rand.

[jadec]

Randomization itself only deal with 2-state values, but you can still use 4-state variables as rand (there are several examples in the spec using "rand integer", for example).