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  1. Thanks for this clarification, it is very useful to me. By the way, why can't I use logic type inside the class? I think I used it many times but never got any compile or any other type of error because of this.
  2. Hi all. I have a question regarding definition of class members: Is it possible to create a field in a class which existence will depend on the value of other field? For example, something like: typedef enum {RED, GREEN, BLUE} color_type; class my_class; color_type my_color; // Only when my_color is RED, I want this class to have another field called my_data if (my_color == RED) then (logic [7:0] my_data); ... endclass: my_class (sorry if any syntax errors) I know this capability exists in e language (by using "when" construct) but I have not been able to find anything
  3. I seems I have included the file with the class two times. Problem solved. Thanks.
  4. Hi, I have the following problem: I have 2 classes: class1 extends uvm_monitor `uvm_component_utils_begin(class1) ... `uvm_component_utils_end ... endclass and second class which extends the previous: class2 extends class1 `uvm_component_utils(class2) ... endclass I am using Cadence irun tool (ncverilog, ncelab), the latest one - incisive 10.20.029 I see warning: Type "class2" is already registered with the factory. I tried using `uvm_component_param_utils instead (in both classes) because this seemed to help in some previous cases I had with parameterized classes,
  5. Hi all. I have a quick question regarding component constructors new() and create(): If, for example, I add initialization of some variables in component's constructor new(), will this initialization be done when I later crate this component using method create()? Basically, will the actions inside the new() method be performed when create method is called to construct the component? Thanks.
  6. Hi Dave. I am using the pre-compiled UVM package. Looking forward to new Questa 10.0b. In the meantime maybe I will check the 6.6e. Thanks for the info.
  7. Hi all. I have been using OVM 2.1.1 until recently and I decided to migrate my environment to UVM 1.0. After doing that I noticed that time required to compile and load the design with QuestaSim 10.0a is much longer than before while I was using OVM 2.1.1. The compilation of files is very slow. Also, loading of the design is very slow. Has anyone else noticed the similar issue? Thanks.
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