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New to UVM - facing problem with Questasim 10.0c

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Hello Friends,

I am new to UVM and very very eager to learn it, I am using windows version of Questasim10.0c, I download the uvm package from accellera. I tried to compile and run code from the the integrated examples - "ubus".

1. Created a project in the below folder "uvm-1.1\examples\integrated\ubus

2. I have added all the files in the folder "uvm-1.1\examples\integrated\ubus\sv"

3. Compiled the files, and facing problems with compilation itself.

errors while trying to compile "ubus_master_driver.sv"

** Error: D:/methodologY/UVM/uvm-1.1/examples/integrated/ubus/sv/ubus_master_driver.sv(28): near "uvm_driver": syntax error, unexpected IDENTIFIER

** Error: D:/methodologY/UVM/uvm-1.1/examples/integrated/ubus/sv/ubus_master_driver.sv(28): Error in class extension specification.

** Error: D:/methodologY/UVM/uvm-1.1/examples/integrated/ubus/sv/ubus_master_driver.sv(37): (vlog-2163) Macro `uvm_component_utils_begin is undefined.

** Error: D:/methodologY/UVM/uvm-1.1/examples/integrated/ubus/sv/ubus_master_driver.sv(37): near "(": syntax error, unexpected '(', expecting function or task.

Please help me out, i am very eager to learn this language.

With Regards


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Thanks for your inputs frodus,

But, i am not using any make file here to compile the files, all i did is just select all the files and did a compile through the GUI, i request you to assist me further on this.

please give me suggestions/inputs on running few examples in my Windows questasim, i do not have access to linux version of questasim.

With Regards


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Look at $QUESTA_HOME/verilog_src/uvm-1.1/examples for a quick Makefile. During our training sessions we face this query often from regular Modelsim/FPGA users and we show them how productive they get with Mkaefiles. BTW on WIndows you can load Cygwin (www.cygwin.com) and use it like UNIX if you wish - that increases productivity by several factors. If you still insist for a traditional GUI based example, drop us an email via http://www.cvcblr.com/about_us - I will ask one of my students to create an example for you.

Good luck

Ajeetha, CVC


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