praneeth Posted June 26, 2015 Report Share Posted June 26, 2015 HI Can any one provide some example for how to get virtual interface in sequence? I need to use the clk in sequece . Thanks praneeth Surya Kiran Muppana 1 Quote Link to comment Share on other sites More sharing options...
ljepson74 Posted June 26, 2015 Report Share Posted June 26, 2015 Praneeth, Try something like this in the sequence: virtual my_if m_my_vif; if (! uvm_config_db#(virtual my_if)::get(uvm_root::get(),"*","somestring",m_my_vif)) `uvm_fatal("config_db"," vif connect failed") Elsewhere, you'd need to have added the handle to the config_db, like so: my_if m_my_if; uvm_config_db#(virtual my_if)::set(uvm_root::get(),"*", "somestring", m_my_if); I haven't compiled this to check for typos. Feedback from gurus welcome. Particularly, I'd like to hear thoughts on having a clock in a sequence. Quote Link to comment Share on other sites More sharing options...
nirmish Posted June 26, 2015 Report Share Posted June 26, 2015 I would recommend to get the get the interface handle inside the sequencer's build phase( the way we do in the monitor & driver) sequence is static block, static in the sense that it will be not be destroyed and created like the sequences. sequences are not extended from the uvm_component so they dont have access to phasing. you can use p_sequencer handle inside the sequences to access the sequence properties, you have to declare the `uvm_declare_p_sequencer(sample_agent_sequencer) inside sequences to access the p_sequencer handle. Thanks Nirmish Quote Link to comment Share on other sites More sharing options...
nirmish Posted June 26, 2015 Report Share Posted June 26, 2015 correction in above statement "sequencer is static block - line2" Quote Link to comment Share on other sites More sharing options...
praneeth Posted June 26, 2015 Author Report Share Posted June 26, 2015 Thanks guys.its working. I get the interface in sequencer and used in sequence. Quote Link to comment Share on other sites More sharing options...
vinitdpatel Posted July 6, 2016 Report Share Posted July 6, 2016 Hi Praneeth, Would you give me example how does you get it worked? Thanks,Vinit Quote Link to comment Share on other sites More sharing options...
vinitdpatel Posted July 6, 2016 Report Share Posted July 6, 2016 Thanks guys.its working. I get the interface in sequencer and used in sequence. Hi Praneeth, would you explain with example if possible how do you get it worked. thanks, Quote Link to comment Share on other sites More sharing options...
c4brian Posted August 3, 2016 Report Share Posted August 3, 2016 class my_sequencer extends uvm_sequencer #(my_txn_type) ; `uvm_component_utils(my_sequencer); virtual interface my_vif; function new(string name, uvm_component parent); super.new(name, parent); endfunction endclass populate my_vif inside the agent, after creating the sequencer. code not shown. access your testbench resource from a sequence: class my_seq extends uvm_sequence #(my_txn_type); `uvm_object_utils(my_seq); `uvm_declare_p_sequencer(my_sequencer); // creates p_sequencer handle function new(string name=""); super.new(name); endfunction virtual task body(); p_sequencer.my_vif.wait_clock(5); // example endtask endclass ps I've run into some opposition on using interface calls in a sequence, but anyway you can use it for accessing other things too. Quote Link to comment Share on other sites More sharing options...
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