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How to get virtual interface in sequence

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Try something like this in the sequence:


virtual  my_if  m_my_vif;


if (! uvm_config_db#(virtual my_if)::get(uvm_root::get(),"*","somestring",m_my_vif))
    `uvm_fatal("config_db"," vif connect failed")
Elsewhere, you'd need to have added the handle to the config_db, like so:
my_if  m_my_if;
uvm_config_db#(virtual my_if)::set(uvm_root::get(),"*", "somestring", m_my_if);
I haven't compiled this to check for typos.
Feedback from gurus welcome.   Particularly, I'd like to hear thoughts on having a clock in a sequence.
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I would recommend to get the get the interface handle inside the sequencer's build phase( the way we do in the monitor & driver)



sequence is static block, static in the sense that it will be not be destroyed and created like the sequences.


sequences are not extended from the uvm_component so they dont have access to phasing.


you can use p_sequencer handle inside the sequences to access the sequence properties, you have to declare the `uvm_declare_p_sequencer(sample_agent_sequencer) inside sequences to access the p_sequencer handle.




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  • 1 year later...
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class my_sequencer extends uvm_sequencer #(my_txn_type) ;

  virtual interface my_vif;

  function new(string name, uvm_component parent);
    super.new(name, parent);


populate my_vif inside the agent, after creating the sequencer.  code not shown.


access your testbench resource from a sequence:

class my_seq extends uvm_sequence #(my_txn_type);
  `uvm_declare_p_sequencer(my_sequencer); // creates p_sequencer handle

  function new(string name="");

  virtual task body();
    p_sequencer.my_vif.wait_clock(5); // example


ps I've run into some opposition on using interface calls in a sequence, but anyway you can use it for accessing other things too.

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