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praneeth

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praneeth last won the day on August 30 2018

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About praneeth

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  1. HI I have two sub modules called A and B within DUT and trying to get register information of both A and B in back door using peek method. I have single ral block which includes both A and B regsiters. I am doing in below way in env. //A registers m.reg_model_h.add_hdl_path(A_HIER) regname=m_reg_model_h.get_reg_by_name("REG_A"); regname.add_hdl_path_slice($sformatf("add_%0d",0),0,5) m_reg_model.lock_model. //B regsiters m.reg_model_h.clear_hdl_path(A_HIER) m.reg_model_h.add_hdl_path(B_HIER) regname=m_reg_model_h.get_reg_by_name("REG_B"); regname.add_hdl_path_slice($sformatf("data_%0d",0),0,5) m_reg_model.lock_model. module dut; A a1; B b1; endmodule When I do the peek of A regsiters I am seeing below error. UVM_ERROR get:unable to locate hdl path test_bencg.dut.b1.add_0. I observed that always B hierarchy overriding when accessing A regsiters. eventhough I provided clear_hdl_path (A_HIER) Can any one please help on this? Thanks, praneeth
  2. Here is the answer. I need to include extended uvm_component(model)type while declaring the port. uvm_analysis_imp_mon#(transaction#(LENGTH),model#(LENGTH) mon_export; Thanks praneeth
  3. Hi, I am seeing member reference resolution error related to uvm_analysis_imp_decl. Linenum52:`uvm_analysis_imp_decl(_mon).Please see in below code. You can see the error as well below which got during elaboration. I tried to connect monitor analysis port to another component analysis export. Giving quick solution is help for me. // Code your testbench here // or browse Examples // Code your testbench here // or browse Examples // Code your testbench here // or browse Examples class transaction #(parameter LENGTH=10) extends uvm_sequence_item; rand bit a; `uvm_object_param_utils_begin(transaction#(LENGTH)) `uvm_field_int(a,UVM_ALL_ON) `uvm_object_utils_end function new(string name="transaction"); super.new(name); endfunction endclass class monitor#(parameter LENGTH=5) extends uvm_monitor#(transaction#(LENGTH)); `uvm_component_param_utils(monitor#(LENGTH)) transaction#(LENGTH) tr; uvm_analysis_port#(transaction#(LENGTH)) analysis_port; function new(string name="monitor",uvm_component parent); super.new(name,parent); endfunction task run_phase(uvm_phase phase); tr=new("mahen"); $display("mahen"); analysis_port.write(tr); endtask endclass Linenum52:`uvm_analysis_imp_decl(_mon) class model#(parameter LENGTH=5) extends uvm_component#(transaction#(LENGTH)); `uvm_component_param_utils(model#(LENGTH)) uvm_analysis_imp_mon#(transaction#(LENGTH)) mon_export; transaction#(LENGTH) tr; function new(string name,uvm_component parent); super.new(name,parent); mon_export=new("mon_export",this); endfunction function write_mon(transaction#(LENGTH) trans); $display("in_monitor"); endfunction endclass class env#(parameter LENGTH=5) extends uvm_component#(transaction#(LENGTH)); `uvm_component_param_utils(env#(LENGTH)) model#(LENGTH) md; monitor#(LENGTH) mon; function new(string name,uvm_component parent); super.new(name,parent); endfunction function build_phase(uvm_phase phase); super.build_phase(phase); md=model#(LENGTH)::type_id::create("model",this); mon=monitor#(LENGTH)::type_id::create("mon",this); endfunction function connect_phase(uvm_phase phase); mon.analysis_port.connect(md.mon_export); endfunction endclass class test#(parameter LENGTH=5) extends uvm_component#(transaction#(LENGTH)); //`uvm_component_param_utils(test#(LENGTH)) typedef uvm_component_registry#(test#(LENGTH),"test") type_id ; env#(LENGTH) en; function new(string name,uvm_component parent); super.new(name,parent); endfunction function build_phase(uvm_phase phase); super.build_phase(phase); en=env#(LENGTH)::type_id::create("env",this); endfunction task run_phase(uvm_phase phase); #10; endtask endclass module top; parameter LENGTH=10; typedef test#(LENGTH) delay_test; initial run_test(); endmodule Parsing design file 'design.sv' Parsing design file 'testbench.sv' Top Level Modules: top Warning-[TMPO] Too many parameter overrides testbench.sv, 31 The extra parameter overrides will be ignored. Source info: uvm_monitor#(transaction#(LENGTH) ) Warning-[TMPO] Too many parameter overrides testbench.sv, 53 The extra parameter overrides will be ignored. Source info: uvm_component#(transaction#(LENGTH) ) Warning-[TMPO] Too many parameter overrides testbench.sv, 76 The extra parameter overrides will be ignored. Source info: uvm_component#(transaction#(LENGTH) ) Warning-[TMPO] Too many parameter overrides testbench.sv, 105 The extra parameter overrides will be ignored. Source info: uvm_component#(transaction#(LENGTH) ) TimeScale is 1 ns / 1 ns Error-[MRRE] Member reference resolution error testbench.sv, 52 Member operator "." cannot be used on object of type int. Expression: m_imp Source info: m_imp.write_mon 4 warnings 1 error CPU time: 3.017 seconds to compile Exit code expected: 0, received Thanks, Preneeth
  4. Thanks guys.its working. I get the interface in sequencer and used in sequence.
  5. HI Can any one provide some example for how to get virtual interface in sequence? I need to use the clk in sequece . Thanks praneeth
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