Nirav Patel Posted July 27, 2011 Report Share Posted July 27, 2011 Hi, In DUT verification environment, From which base class should reference_model class be derived? or the logic of that reference model should be part of monitor? what UVM methodology says about this? Thanks, Nirav Quote Link to comment Share on other sites More sharing options...
dave_59 Posted July 27, 2011 Report Share Posted July 27, 2011 The reference module should be part of the scoreboard or between the monitor and scoreboard. You might want to check out the Verification Academy section on scoreboards for some examples. http://www.verificationacademy.com/uvm-ovm/Tour/Analysis Quote Link to comment Share on other sites More sharing options...
uwes Posted July 28, 2011 Report Share Posted July 28, 2011 hi, a typical standalone reference model would most likely be dervied from uvm_component. it should not be part of the monitor. monitors and drivers translate transactions into bit-wiggle (and reverse). /uwe Quote Link to comment Share on other sites More sharing options...
Praveen Chenna Posted July 28, 2011 Report Share Posted July 28, 2011 Hi, To provide a good level of abstraction, reference model should be a class derived from uvm_component and with proper port/export mechanism with required analysis components in the environment. The referecence model should 'get' the configuration discriptor/object from the uvm configration date base. Regards, Praveen. Quote Link to comment Share on other sites More sharing options...
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