roginski Posted May 25, 2011 Report Share Posted May 25, 2011 Hi. I am a newcomer to SystemVerilog and UVM, having used Vera for many years. One thing I'm struggling with is testbench timing. The Chris Spear book, 'SystemVerilog for Verification' suggests using program blocks for testbench to avoid race conditions between design and testbench. The VMM examples use program blocks, and clocking blocks to control timing of stimulus. But the UVM examples don't. They put the testbench in a regular verilog module. Also the UVM doc has nothing to say about timing... somehow it is a non-issue. I'm writing to ask people that have had more experience writing UVM testbenches. Should I be worried about race conditions? What should I do to avoid them? Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.