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Testbench/design race conditions; program blocks; clocking blocks

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Hi. I am a newcomer to SystemVerilog and UVM, having used

Vera for many years. One thing I'm struggling with

is testbench timing. The Chris Spear book, 'SystemVerilog for

Verification' suggests using program blocks for testbench

to avoid race conditions between design and testbench.

The VMM examples use program blocks, and clocking blocks

to control timing of stimulus. But the UVM examples don't.

They put the testbench in a regular verilog module. Also the

UVM doc has nothing to say about timing... somehow it is a non-issue.

I'm writing to ask people that have had more experience writing

UVM testbenches. Should I be worried about race conditions?

What should I do to avoid them?

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