Jump to content


  • Posts

  • Joined

  • Last visited

roginski's Achievements


Member (1/2)



  1. I'm generating ethernet packets, they need a 32-bit crc on the end. Another question, is there an example of a UVM testbench for a networking device? Send packets into a port, receive packets back out, and check them?
  2. I'm switching from Vera to SystemVerilog/UVM. Vera had a handy function called vera_crc that calculated crc's. What do SystemVerilog folks use? Thanks, -K
  3. Hi. I am a newcomer to SystemVerilog and UVM, having used Vera for many years. One thing I'm struggling with is testbench timing. The Chris Spear book, 'SystemVerilog for Verification' suggests using program blocks for testbench to avoid race conditions between design and testbench. The VMM examples use program blocks, and clocking blocks to control timing of stimulus. But the UVM examples don't. They put the testbench in a regular verilog module. Also the UVM doc has nothing to say about timing... somehow it is a non-issue. I'm writing to ask people that have had more experience writing UVM testbenches. Should I be worried about race conditions? What should I do to avoid them?
  • Create New...