jsree Posted May 16, 2011 Report Share Posted May 16, 2011 Hi As per the uvm_users_guide_1.0.pdf (dated Feb 23, 2011) at Page 190 on Virtual Sequencer example shows The following example declares a virtual sequencer with two subsequencers. Two interfaces called eth and cpu are created in the build function, which will be hooked up to the actual sub-sequencers. class simple_virtual_sequencer extends uvm_sequencer; eth_sequencer eth_seqr; cpu_sequencer cpu_seqr; // Constructor function new(input string name="simple_virtual_sequencer", input uvm_component parent=null); super.new(name, parent); // Automation macro for virtual sequencer (no data item) `uvm_update_sequence_lib endfunction // UVM automation macros for sequencers `uvm_sequencer_utils(simple_virtual_sequencer) endclass: simple_virtual_sequencer so when I tried the `uvm_update_sequence_lib in testebench got following error Identifier 'uvm_update_sequence_lib' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. and 'uvm_update_sequence_lib is missing uvm_class_reference_Manual_1.0.pdf Any idea ? Jay Quote Link to comment Share on other sites More sharing options...
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