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Adam Sherilog

UVM Reference Flow updated to UVM 1.0

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The UVM Reference Flow version 1.02 has been updated to align with the Accellera uvm-1.0 release (uvm-1.0p1). It applies the Universal Verification Methodology (UVM) to a block and cluster verification in a SoC design. The UVM Reference Flow was developed by Cadence to show the best practices for applying UVM to the verification of a block; a Universal Asynchronous Receiver Transmitter (UART). It then shows how to reuse the block level verification environment when verifying a cluster design (an APB subsystem) into which the UART is integrated along with other design components (viz. SPI, GPIO, power controller, timers etc.).

You can download this open source contribution here on UVMWorld.

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Hi,

I attempted to compile the UVM reference flow "uart_subsystem" using Makefile / filelists that I received from Srini /Ajeetha (CVCBlr). However, there seems to be an issue in the UVM RGM package, I tried using UVM EA kit (uvm-1.0p1) and also with the later release (uvm-1.1a). However the same error shows up in both the cases. The error :

** Error: ../soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_pkg.sv(36): Could not find the package (uvm_rgm_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.

-- Importing package apb_pkg

-- Importing package uart_pkg

** Error: ../soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv//uart_ctrl_regs.sv(21): near "uvm_rgm_sized_regist": syntax error, unexpected "IDENTIFIER"

** Error: ../soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv//uart_ctrl_regs.sv(21): Error in class extension specification.

** Error: ../soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv//uart_ctrl_regs.sv(34): (vlog-2163) Macro `uvm_rgm_fld_utils_begin is undefined.

** Error: ../soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv//uart_ctrl_regs.sv(34): near "(": syntax error, unexpected '(', expecting "function" or "task"

-- Compiling package gpio_pkg

** Error: ../soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv//uart_ctrl_scoreboard.sv(34): near "p": syntax error, unexpected "IDENTIFIER", expecting "class"

** Error: ../soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_pkg.sv(57): near "package": syntax error, unexpected "package", expecting "IDENTIFIER" or "TYPE_IDENTIFIER"

.

Thanks

Girish

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The error log that I get while attempting to compile UVM RGM with UVM 1.0p1 is:

QuestaSim vlog 6.6b Compiler 2010.05 May 21 2010

-- Compiling package uvm_pkg

-- Compiling package uvm_rgm_pkg

-- Importing package uvm_pkg

** Error: ../uvm_rgm/sv/uvm_rgm_base.sv(88): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_base.sv(148): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_base.sv(152): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_base.sv(159): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_base.sv(164): Field/method name (print_footer) not in 'printer'

** Error: ../uvm_rgm/sv/uvm_rgm_container.sv(212): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_container.sv(239): Field/method name (print_footer) not in 'printer'

** Error: ../uvm_rgm/sv/uvm_rgm_container.sv(250): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_container.sv(252): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_container.sv(259): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_container.sv(266): Field/method name (print_footer) not in 'printer'

** Error: ../uvm_rgm/sv/uvm_rgm_sized_register.sv(205): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_sized_register.sv(226): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_fifo_register.sv(189): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_memory.sv(233): Number of actuals and formals does not match in function call.

** Error: ../uvm_rgm/sv/uvm_rgm_sequencer.sv(155): (vlog-7027) Dotted name ('choose_next_request') not found in current scope. Note that hierarchical references are not allowed from within a package or $unit.

** Error: ../uvm_rgm/sv/uvm_rgm_sequencer.sv(157): (vlog-7027) Dotted name ('wait_for_available_sequence') not found in current scope. Note that hierarchical references are not allowed from within a package or $unit.

** Error: ../uvm_rgm/sv/uvm_rgm_sequencer.sv(162): (vlog-7027) Dotted name ('set_arbitration_completed') not found in current scope. Note that hierarchical references are not allowed from within a package or $unit.

-- Compiling package uvm_config_prop_pkg

-- Compiling package ahb_pkg

-- Importing package uvm_config_prop_pkg

-- Compiling package apb_pkg

-- Compiling package uart_pkg

-- Compiling package uart_ctrl_pkg

** Error: ../soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_pkg.sv(36): Could not find the package (uvm_rgm_pkg). Design read will......

Would someone have a working version of the UVM Reference flow for Mentor Questa?

-ghalady

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You may need to download the UVM_RGM package from the user contribution section of UVMWorld and add that to your compilation scripts. The UVM_RGM package is not part of the officially released UVM package, it is a user contribution from Cadence. The standard UVM package contains uvm_reg, that was officially released with UVM 1.1. If you are just looking for examples to learn the UVM that already work with Questa, I suggest looking here.

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I see you found the package as I was typing my last message. I would make sure the release of uvm_rgm that you are using matches the release of the UVM that you have. Again, I strongly recommend using uvm_reg.

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