Different packet types with single sequencer.?

[Balakasaiah]

Hi,

 

  Here I am attaching a sample code for my doubt:

 

1)  class base_pkt extends uvm_sequence_items;

     -

     -

    endclass

 

2)  class base1_pkt extends base_pkt;

     -

     -

     endclass

 

3)  class base2_pkt extends base1_pkt;

     -

     -

     endclass

 

4) class my_sqr extends uvm_sequencer#(base_pkt);

     -

     -

     endclass

 

    There are sequences for each packet like seq_base_pkt, seq_base1_pkt, seq_base2_pkt.

    The corresponding transaction types provided for the sequences.

 

    Q:- When I run this code by adding required structure. Can I be able to generate all packets to driver through sequencer..?

 

Regards,

Balakasaiah.

 

 

 

[mihaistoian_amiq]

Hi,

 

   You can generate any packet derived from a base packet once you register the derived packets with the factory.

   Use the  "create" method to obtain the desired packet type:

   

    //derived packet type

    class base1_pkt extends base_pkt;

       //register through the macro

       `uvm_object_utils(base1_pkt)

       ...

    endclass

 

   

    class test extends uvm_test;

        ...

        task run_phase();

           //use "create" to get the derived packet you want

           base_pkt  pkt = base1_pkt::type_id::create("");

           ....

        endtask

    endclass

[David Black]

Keep in mind that if you add any fields the driver needs to see, they must be present in the base_pkt -OR- there must be some base_pkt methods that provide access via some type of return value.

[Balakasaiah]

Thanks David Black.

[Balakasaiah]

Why don't can we access the variables in the base1_pkt..?

 

Any way we are creating the object of base1_pkt. Bcz, the object created will allocate all the variables in the base1_packet.

 

If Yes, the same object (pkt) is sent to the driver where driver can also access the fields of base1_pkt.

 

Ex:   

    class base1_pkt extends base_pkt;

       int a;

       -

     endclass

 

    class test extends uvm_test;

        ...

        task run_phase();

           //use "create" to get the derived packet you want

           base_pkt  pkt = base1_pkt::type_id::create("");

           pkt.a = 10; // Is it not possible..?

           ....

        endtask

    endclass

 

Regards,

Balakasaiah.

[Balakasaiah]

I would like to ask one more question.

 

Can we declare a blocking port of type base packet on which both base and derived packets needs to be sent...?

 

 

Regards,

Balakasaiah.

[mihaistoian_amiq]

Hi Balakasaiah,

 

 

   About your last code example : 

 

    class base1_pkt extends base_pkt;

       int a;

       -

     endclass

 

    class test extends uvm_test;

        ...

        task run_phase();

           //use "create" to get the derived packet you want

           base_pkt  pkt = base1_pkt::type_id::create("");

           pkt.a = 10; // Is it not possible..?

           ....

        endtask

    endclass

 

    If you want to access fields defined in the derived packet you can do it through the $cast() function : 

 

      class test extends uvm_test;

        ...

        task run_phase();

           //define a base1_pkt variable

           base1_pkt pkt1;

 

           //use "create" to get the derived packet you want

           base_pkt  pkt = base1_pkt::type_id::create("");

 

           $cast(pkt1 , pkt)

           pkt1.a = 10; // this should work now

           ....

        endtask

    endclass

[Balakasaiah]

Thank you so much...