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About Balakasaiah

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  • Birthday 12/11/1990

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  1. I would like to ask one more question. Can we declare a blocking port of type base packet on which both base and derived packets needs to be sent...? Regards, Balakasaiah.
  2. Why don't can we access the variables in the base1_pkt..? Any way we are creating the object of base1_pkt. Bcz, the object created will allocate all the variables in the base1_packet. If Yes, the same object (pkt) is sent to the driver where driver can also access the fields of base1_pkt. Ex: class base1_pkt extends base_pkt; int a; - endclass class test extends uvm_test; ... task run_phase(); //use "create" to get the derived packet you want base_pkt pkt = base1_pkt::type_id::create(""); p
  3. Hi, Here I am attaching a sample code for my doubt: 1) class base_pkt extends uvm_sequence_items; - - endclass 2) class base1_pkt extends base_pkt; - - endclass 3) class base2_pkt extends base1_pkt; - - endclass 4) class my_sqr extends uvm_sequencer#(base_pkt); - - endclass There are sequences for each packet like seq_base_pkt, seq_base1_pkt, seq_base2_pkt. The corresponding transaction types provided for the sequences. Q:- When I run this code by adding required structure. Can
  4. Thanks Ralph, I have got it..... I have made a mistake in using parameter names...
  5. I am exactly doing the same.... But getting compilation error...
  6. I am doing port binding as follows: In Top Module: a2a_tc.bid( sig_bid); // Error is Showing for this line wrf.BID( sig_bid ); a2a_tc, wrf are modules, bid is an output port of a2a_tc, i.e sc_out<sc_uint<4> > bid; // Here the 4 value is parameterised and is sent to two modules while instantiation BID is an input port of wrf, i.e sc_in<sc_uint<4> > BID; sig_bid is a signal. i.e sc_signal<sc_uint<4> > sig_bid; instantiations are: a2a_mod<WIDTH> a2a_tc; write_mod<WIDTH&
  7. Error Message is: no match function call to '(sc_core::sc_out<sc_dt::sc_uint<4> >) (int &)'
  8. Ralph, I have tried as you said.. But, I am getting error from the top module saying "no match fo call to.........", the error is for parameterzed ports only, for other ports it is not showing any compilation error.....
  9. Hi, I have to instantiate a module multiple times. The Sample code is as below: #define BUS_WIDTH1 32 #define BUS_WIDTH2 16 SC_MODULE( mymod ) { sc_in<sc_bv<BUS_WIDTH1> > din; sc_out<sc_bv<BUS_WIDTH2> > dout; sub_mod s1; SC_CTOR( mymod ): s1(BUS_WIDTH2) { // Port Connections } }; SC_MODULE( sub_mod ) { sc_in<sc_bv<BUS_WIDTH> > in; . . SC_HAS_PROCESS( sub_mod); sub_mod(sc_module_name nm,int BUS_WIDTH):sc_module(nm) { } }; I am passing
  10. In blocking transport calls we are sending delay also. What is the real usage of it.....? Why an initiator is sending the delay instead the target adding it's own delay.....?
  11. I have changed the parameter 'tlm::tlm_generic_payload' to 'tlm::tlm_generic_payload &' in the implementation of b_transport method. Now it is working fine.
  12. I am calling it from the Constructor of Target class. and the call is as follows: trg_socket.register_b_transport(this, &Target::b_transport); // Target is a target class name, trg_socket is an instance of the target socket
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