Vithal Posted March 13, 2015 Report Share Posted March 13, 2015 I am trying to use uvm reg in SOC to load initial programming of clocks & other csr programming by backdoor loading, it reduced the simulator time but the wall clock time is increased much compared to the frontdoor programming. Removed uvm reg factory registration for all the regs, removed all the fields, replace create with new and only kept hdl_paths & memory map related assignments, now the wall clk time is reduced by 50% but still backdoor sim wall clk time is more than the fron door. tried assigning null to the ral_env once the backdoor programming is done still no change. Any one has faced this problem? any solution to over come this? following is the tests sim data: with frotdoor --> took 3msec --> 1hr30mins with backdoor(+with all the above optimisation) --> took 2msec --> 3hrs (sim till the backdoor completion took only 14mins, but rest of the sim perf is badly affected) My basic question is , once my backdoor is done, i am assigning null to the ral_env, is the ral_env obj not going into auto garbagecollection and not freeing the memory? We have total 850 registers in my ral_env, all the regs doesn't have any fields also. Adavance thanks for your input/suggestion. Thanks, Vithal Quote Link to comment Share on other sites More sharing options...
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