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  1. hi, Thanks for you suggestions/time & sorry for the late reply. After doing the profiling, figured out the there is a configuration issue with & without backdoor simulations. In frontdoor simulation we are enabling few clks but where as in bkdoor sim we are enabling all theSOC clocks. After correcting this we see SOC sim time improvements in back door sims. Thanks a lot for the support. Regards, Vithal
  2. hi, ok, for vcs i am using the following access options: $init_signal_spy call=Mhdl_Xmr_call check=Mhdl_Xmr_check acc+=rw:* acc+=rw,wn,frc:* acc+=cbk:*
  3. Hi, Sorry for the late reply. tried vcs mem/time profiling but not able to analyse it correctly as the report is a summary at the end of the sim, instead of which sim time it took more mem. I tried with MTI also and seeing the same perf issue, so it is not tool issue, it is UVM issue(collecting the garbage/cleaning the unreferenced object not cleaned) following is my test data: Front door: test took 1.8ms sim time and 1hr 6mins wall clock time. backdoor sim: 0 -- 114usec --> backdoor init configuration done -->took ~10mins --> after this deleted the regblock(reg_env has as
  4. I am trying to use uvm reg in SOC to load initial programming of clocks & other csr programming by backdoor loading, it reduced the simulator time but the wall clock time is increased much compared to the frontdoor programming. Removed uvm reg factory registration for all the regs, removed all the fields, replace create with new and only kept hdl_paths & memory map related assignments, now the wall clk time is reduced by 50% but still backdoor sim wall clk time is more than the fron door. tried assigning null to the ral_env once the backdoor programming is done still no change. A
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